aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-02-21 17:36:51 +0100
committerClifford Wolf <clifford@clifford.at>2019-02-21 17:40:52 +0100
commit28fba903c595710c401a6c7d49e7bfd3f8c64efc (patch)
treec7f7d9c96f4bf24b023716311d9668e777e0e263
parent31fea5eb33a5f2feef65b38df869fed217323fb6 (diff)
downloadyosys-28fba903c595710c401a6c7d49e7bfd3f8c64efc.tar.gz
yosys-28fba903c595710c401a6c7d49e7bfd3f8c64efc.tar.bz2
yosys-28fba903c595710c401a6c7d49e7bfd3f8c64efc.zip
Fix segfault in printing of some internal error messages
Signed-off-by: Clifford Wolf <clifford@clifford.at>
-rw-r--r--frontends/ast/genrtlil.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e66625228..bdc34d490 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -792,7 +792,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// everything should have been handled above -> print error if not.
default:
for (auto f : log_files)
- current_ast->dumpAst(f, "verilog-ast> ");
+ current_ast_mod->dumpAst(f, "verilog-ast> ");
log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
}
@@ -1565,7 +1565,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// everything should have been handled above -> print error if not.
default:
for (auto f : log_files)
- current_ast->dumpAst(f, "verilog-ast> ");
+ current_ast_mod->dumpAst(f, "verilog-ast> ");
type_name = type2str(type);
log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
}