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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 18:58:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-21 18:58:44 +0100 |
| commit | 0e371109b03b7700b22fedcd96e9508a01f2b662 (patch) | |
| tree | 1fce3fcd7e70d99024b8939c6ee13ad745b5b1c2 | |
| parent | 03aa3541aeff0ff372672f553c114fb4146c7858 (diff) | |
| parent | 2da4c9c8f0a849434f657ac4a56de11d35e1c41e (diff) | |
| download | yosys-0e371109b03b7700b22fedcd96e9508a01f2b662.tar.gz yosys-0e371109b03b7700b22fedcd96e9508a01f2b662.tar.bz2 yosys-0e371109b03b7700b22fedcd96e9508a01f2b662.zip | |
Merge pull request #818 from YosysHQ/clifford/dffsrfix
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 5880254c1..e8570f0eb 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } else { @@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetParam("\\CLR_POLARITY"); cell->unsetPort("\\SET"); cell->unsetPort("\\CLR"); - - return true; } + + return true; } - else + + if (!hasreset) { IdString new_type; @@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) cell->unsetPort("\\S"); cell->unsetPort("\\R"); - return did_something; + return true; } + + return did_something; } bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch) |