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* ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-032-9/+31
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* memory_map: add -attr option, to respect inference attributes.whitequark2020-04-031-6/+113
| | | | | | | | | | | | | | | | | | | Before this commit, memory_map (which is always a part of a synth script) would always pick up any $mem cell that was not processed by a preceding pass and lower it down to $dff/$mux cells. This is undesirable for two reasons: * If there is an explicit inference attribute set on a $mem cell, e.g. (* ram_block *), then it is arguably incorrect to map such a memory to $dff/$mux cells. * If memory_map tries to lower a memory that was intended to be mapped to a large BRAM, it often takes extraordinarily long time to finish, produces an extremely large log file, and outputs an unusable design. After this commit, properly invoked memory_map will not map any memory that has an explicit inference attribute specified, solving the first issue, and alleviating the second. The default behavior is not changed.
* ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-065-5/+376
| | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* ice40: match memory inference attribute values case insensitive.whitequark2020-02-062-0/+7
| | | | LSE/Synplify use case insensitive matching.
* memory_bram: add `attr_icase` option.whitequark2020-02-061-7/+35
| | | | | Some vendor toolchains use case insensitive matching for values of attributes that control BRAM inference.
* ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-064-20/+238
| | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* Merge pull request #1682 from YosysHQ/eddie/opt_after_techmapEddie Hung2020-02-058-5/+9
|\ | | | | synth_*: call 'opt -fast' after 'techmap'
| * synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-053-2/+14
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* Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-052-1/+65
|\ | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-28190-4933/+9266
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| * | Add $_FF_ and $_SR* courtesy of @mwkmwkmwkEddie Hung2019-12-202-23/+33
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| * | More stringent check for flop cellsEddie Hung2019-12-201-2/+4
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| * | opt_merge to discard \init of '$' cells with 'Q' port when mergingEddie Hung2019-12-131-0/+11
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| * | Add testcaseEddie Hung2019-12-131-0/+49
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* | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-054-39/+185
|\ \ \ | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0577-1944/+4467
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| * | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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| * | | | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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| * | | | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
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| * | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-214-77/+73
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| * | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-213-0/+149
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* | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-052-2/+22
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* | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-052-6/+143
|\ \ \ \ | | | | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | | More rigorous testEddie Hung2020-01-161-7/+34
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| * | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-152-6/+116
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* | | | | Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-0512-242/+809
|\ \ \ \ \ | | | | | | | | | | | | abc9: add support for required times
| * | | | | abc9_ops: -check for negative arrival/required timesEddie Hung2020-01-271-4/+22
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| * | | | | Fix typoEddie Hung2020-01-271-1/+1
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| * | | | | Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-2726-246/+537
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-153-3/+16
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| * | | | | | | Update README.md for (* abc9_required *)Eddie Hung2020-01-151-4/+9
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| * | | | | | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-154-4/+4
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+2
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| * | | | | | | | abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)Eddie Hung2020-01-142-3/+3
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| * | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-27/+19
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| * | | | | | | | | abc9_ops: -check to check abc9_{arrival,required}Eddie Hung2020-01-141-3/+30
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| * | | | | | | | | abc9_ops: implement a requireds_cacheEddie Hung2020-01-141-26/+34
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| * | | | | | | | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-143-78/+106
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| * | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-10/+1
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | | | | | abc9_ops: fix -reintegrate handling of $__ABC9_DELAYEddie Hung2020-01-141-2/+3
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| * | | | | | | | | | abc9_ops: -prep_times -> -prep_delays; add docEddie Hung2020-01-142-11/+23
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| * | | | | | | | | | abc9_ops: cleanupEddie Hung2020-01-141-14/+5
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| * | | | | | | | | | abc9_ops: discard $__ABC9_DELAY boxesEddie Hung2020-01-141-7/+2
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| * | | | | | | | | | write_xaiger: skip if no arrival timesEddie Hung2020-01-141-0/+3
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| * | | | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-1422-389/+789
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-1211-156/+198
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | | | | | | | log_debug() for abc9_{arrival,required} timesEddie Hung2020-01-102-1/+15
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| * | | | | | | | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
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