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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:30:39 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:30:39 -0800 |
| commit | e0bdf5d7a9280c9f975a34fc265793de86fd9bec (patch) | |
| tree | 4d25166df88e7fc302ca889d65b80198a995dac4 | |
| parent | f2576c096cedf0974f237530a9d50e250bf117a3 (diff) | |
| download | yosys-e0bdf5d7a9280c9f975a34fc265793de86fd9bec.tar.gz yosys-e0bdf5d7a9280c9f975a34fc265793de86fd9bec.tar.bz2 yosys-e0bdf5d7a9280c9f975a34fc265793de86fd9bec.zip | |
Fix typo
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -378,7 +378,7 @@ Verilog Attributes and non-standard features port. It can be used, for example, to specify the clk-to-Q delay of a flip- flop output for consideration during `abc9` techmapping. -- The input port attribute ``abc9_requiredl`` specifies an integer, or a string +- The input port attribute ``abc9_required`` specifies an integer, or a string of space-separated integers to be used as the required time of this blackbox port. It can be used, for example, to specify the setup-time of a flip-flop input for consideration during `abc9` techmapping. |