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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 07:20:06 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-02-06 14:58:20 +0000 |
| commit | 3f4460a1869ccfd6225379d18ade195f165841a4 (patch) | |
| tree | 6ddcfe6d74e59ebda5fef41e27c715df20f42da2 | |
| parent | 60f047f13606554cf800603580fd464d5764a174 (diff) | |
| download | yosys-3f4460a1869ccfd6225379d18ade195f165841a4.tar.gz yosys-3f4460a1869ccfd6225379d18ade195f165841a4.tar.bz2 yosys-3f4460a1869ccfd6225379d18ade195f165841a4.zip | |
ice40: match memory inference attribute values case insensitive.
LSE/Synplify use case insensitive matching.
| -rw-r--r-- | techlibs/ice40/brams.txt | 1 | ||||
| -rw-r--r-- | tests/arch/ice40/memories.ys | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt index d51c7119a..36dfddab2 100644 --- a/techlibs/ice40/brams.txt +++ b/techlibs/ice40/brams.txt @@ -30,6 +30,7 @@ endbram # The syn_* attributes are described in: # https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx +attr_icase 1 match $__ICE40_RAM4K_M0 # implicitly requested RAM or ROM diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 83386f0ec..43bcf2452 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -36,6 +36,12 @@ select -assert-count 1 t:SB_RAM40_4K design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "Block_RAM" m:memory +synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp +select -assert-count 1 t:SB_RAM40_4K # any case works + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K |