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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 13:13:15 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 13:13:15 -0800 |
| commit | 593897ffc0b7bedfd65cdddf68dee6b89295b70b (patch) | |
| tree | f998d71484cd1359f7fa5068d8f051e9c899145d | |
| parent | 300003cb7854650cab9dd063a864f8f1df052d6d (diff) | |
| download | yosys-593897ffc0b7bedfd65cdddf68dee6b89295b70b.tar.gz yosys-593897ffc0b7bedfd65cdddf68dee6b89295b70b.tar.bz2 yosys-593897ffc0b7bedfd65cdddf68dee6b89295b70b.zip | |
abc9_ops: cleanup
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index e1f6252f2..9b7901ffb 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -233,25 +233,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto w = inst_module->wire(port_name); log_assert(w); if (w->get_bool_attribute("\\abc9_carry")) { - if (w->port_input) { - if (carry_in != IdString()) - log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module)); + log_assert(w->port_input != w->port_output); + if (w->port_input) carry_in = port_name; - } - if (w->port_output) { - if (carry_out != IdString()) - log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module)); + else if (w->port_output) carry_out = port_name; - } } else r.first->second.push_back(port_name); } - - if (carry_in != IdString() && carry_out == IdString()) - log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module)); - if (carry_in == IdString() && carry_out != IdString()) - log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module)); if (carry_in != IdString()) { r.first->second.push_back(carry_in); r.first->second.push_back(carry_out); @@ -723,9 +713,10 @@ void reintegrate(RTLIL::Module *module) auto w = box_module->wire(port_name); log_assert(w); if (w->get_bool_attribute("\\abc9_carry")) { + log_assert(w->port_input != w->port_output); if (w->port_input) carry_in = port_name; - if (w->port_output) + else if (w->port_output) carry_out = port_name; } else |