| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | write_xaiger to support part-selected modules again | Eddie Hung | 2019-12-05 | 1 | -11/+37 | |
| * | | | | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 | |
| * | | | | | Remove clkpart | Eddie Hung | 2019-12-05 | 3 | -313/+0 | |
| * | | | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 | |
| * | | | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 | |
| * | | | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 2 | -118/+292 | |
| * | | | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 | |
| * | | | | | Bump ABC to get "&verify -s" fix | Eddie Hung | 2019-12-04 | 1 | -1/+1 | |
| * | | | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 | |
| * | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 | |
| * | | | | | Cleanup | Eddie Hung | 2019-12-03 | 1 | -11/+12 | |
| * | | | | | Add assertion | Eddie Hung | 2019-12-03 | 1 | -0/+1 | |
| * | | | | | write_xaiger to consume abc9_init attribute for abc9_flops | Eddie Hung | 2019-12-03 | 1 | -34/+28 | |
| * | | | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 2 | -4/+24 | |
| * | | | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 | |
| * | | | | | Update ABCREV for upstream bugfix | Eddie Hung | 2019-12-03 | 1 | -1/+1 | |
| * | | | | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
| * | | | | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 | |
| * | | | | | Cleanup | Eddie Hung | 2019-12-01 | 1 | -3/+2 | |
| * | | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-01 | 1 | -1/+1 | |
| * | | | | | Use pool<> not std::set<> for determinism | Eddie Hung | 2019-12-01 | 1 | -4/+4 | |
| * | | | | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
| * | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
| |\ \ \ \ \ | ||||||
| | * | | | | | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 | |
| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
| |\| | | | | | ||||||
| | * | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
| | * | | | | | Add multiple driver testcase | Eddie Hung | 2019-11-27 | 1 | -0/+31 | |
| * | | | | | | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 | |
| * | | | | | | Add comment, use sigmap | Eddie Hung | 2019-11-27 | 1 | -2/+2 | |
| * | | | | | | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-27 | 5 | -7/+100 | |
| |\ \ \ \ \ \ | | |/ / / / | |/| | | | | ||||||
| | * | | | | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd | Eddie Hung | 2019-11-27 | 2 | -3/+72 | |
| | |\ \ \ \ \ | ||||||
| | | * | | | | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | | * | | | | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 | |
| | | * | | | | | Check for either sign or zero extension for postAdd packing | Eddie Hung | 2019-11-26 | 1 | -3/+3 | |
| | | * | | | | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 | |
| | | | |/ / / | | |/| | | | ||||||
| | * | | | | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attr | Clifford Wolf | 2019-11-27 | 1 | -0/+4 | |
| | |\ \ \ \ \ | ||||||
| | | * | | | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| | * | | | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 | |
| | |\ \ \ \ \ \ | ||||||
| | | * | | | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 2 | -4/+24 | |
| | | | |/ / / / | | |/| | | | | ||||||
| | * | | | | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve | Eddie Hung | 2019-11-27 | 2 | -22/+5 | |
| | |\ \ \ \ \ \ | | |/ / / / / | |/| | | | | | ||||||
| * | | | | | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
| * | | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-27 | 1 | -7/+3 | |
| |\ \ \ \ \ \ \ | | |_|_|/ / / | |/| | | | | | ||||||
| | * | | | | | | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 | |
| * | | | | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 4 | -34/+30 | |
| |\ \ \ \ \ \ \ | | |_|/ / / / | |/| | | | | | ||||||
| | * | | | | | | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
| | * | | | | | | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 | |
| | * | | | | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
| | | |/ / / / | |/| | | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |