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* Merge branch 'xaig' into xc7muxEddie Hung2019-05-315-15/+99
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| * Fix abc9 with (* keep *) wiresEddie Hung2019-04-232-6/+52
| * Move clean from aigerparse to abc9Eddie Hung2019-04-232-2/+1
| * Use nonblockingEddie Hung2019-04-231-1/+1
| * Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-228-41/+382
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| | * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-228-41/+382
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| * | | Tidy upEddie Hung2019-04-222-7/+1
| * | | Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-222-7/+95
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* | | Throw out unused code inherited from abcEddie Hung2019-05-311-212/+3
* | | Fix issue where keep signal became PI, but also box was adding CI driverEddie Hung2019-05-301-5/+19
* | | read_xaiger() to name box signalsEddie Hung2019-05-301-4/+8
* | | Fix spellingEddie Hung2019-05-301-1/+1
* | | Remove whitebox attribute from DRAMs for nowEddie Hung2019-05-301-2/+2
* | | Do not re-sort box_module portsEddie Hung2019-05-301-4/+6
* | | Remove whitespaceEddie Hung2019-05-301-1/+0
* | | Revert "Re-enable &dc2"Eddie Hung2019-05-301-1/+1
* | | Do not double count LUT1sEddie Hung2019-05-301-1/+0
* | | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-304-12/+91
* | | Re-enable &dc2Eddie Hung2019-05-301-1/+1
* | | Reduce -W to 160Eddie Hung2019-05-291-1/+1
* | | Some more realistic delays...Eddie Hung2019-05-291-7/+7
* | | Erase all boxes before stitchingEddie Hung2019-05-291-27/+30
* | | Call &if with -W 250Eddie Hung2019-05-291-1/+6
* | | Bump ABCEddie Hung2019-05-291-1/+1
* | | Rename to #23Eddie Hung2019-05-291-3/+3
* | | Add abc_test024Eddie Hung2019-05-291-6/+19
* | | Fix abc_test024Eddie Hung2019-05-291-4/+5
* | | Add some debug to abc9Eddie Hung2019-05-291-1/+19
* | | Add abc9_test022Eddie Hung2019-05-281-0/+22
* | | Fix for abc9_test022Eddie Hung2019-05-281-2/+6
* | | Small improvementEddie Hung2019-05-281-4/+2
* | | From masterEddie Hung2019-05-281-1/+1
* | | From masterEddie Hung2019-05-281-1/+1
* | | TypoEddie Hung2019-05-281-1/+1
* | | Update from masterEddie Hung2019-05-285-64/+59
* | | Update README.md from masterEddie Hung2019-05-281-3/+3
* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-2817-104/+422
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| * \ \ Merge pull request #1050 from YosysHQ/clifford/wandworClifford Wolf2019-05-289-40/+207
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| | * | | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-283-103/+145
| | * | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| | * | | Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandworClifford Wolf2019-05-288-5/+127
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| | | * \ \ Merge branch 'master' into wandworStefan Biereigel2019-05-2715-32/+274
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| | | * | | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
| | | * | | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
| | | * | | | update README.md with wand/wor informationStefan Biereigel2019-05-271-2/+2
| | | * | | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
| | | * | | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-272-98/+91
| | | * | | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
| | | * | | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
| | | * | | | fix indentation across filesStefan Biereigel2019-05-234-63/+83