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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 12:25:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 12:25:21 -0700 |
| commit | c6fa4faa371ad3dbefe4c57bd758942e461869da (patch) | |
| tree | 9401c9079cd7f2145a2552a8c61191638392925c | |
| parent | a44fe3a632f6beafe0ba2831bba06bf855d7e89d (diff) | |
| download | yosys-c6fa4faa371ad3dbefe4c57bd758942e461869da.tar.gz yosys-c6fa4faa371ad3dbefe4c57bd758942e461869da.tar.bz2 yosys-c6fa4faa371ad3dbefe4c57bd758942e461869da.zip | |
Remove whitespace
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 915c53a1b..7adfacb53 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -683,7 +683,6 @@ void AigerReader::post_process() } } - // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { |