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author | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 13:42:42 +0200 |
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committer | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 13:57:27 +0200 |
commit | c2caf85f7cbcbea4240b56a134e4c3e74189c62d (patch) | |
tree | 8734d328465f28cbcb5be7796a36295e473ff031 | |
parent | fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae (diff) | |
download | yosys-c2caf85f7cbcbea4240b56a134e4c3e74189c62d.tar.gz yosys-c2caf85f7cbcbea4240b56a134e4c3e74189c62d.tar.bz2 yosys-c2caf85f7cbcbea4240b56a134e4c3e74189c62d.zip |
add simple test case for wand/wor
-rw-r--r-- | tests/various/wandwor.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v new file mode 100644 index 000000000..824f89683 --- /dev/null +++ b/tests/various/wandwor.v @@ -0,0 +1,35 @@ +module a(Q); + output wire Q; + + assign Q = 0; +endmodule + +module b(D); + input wire D; +endmodule + +module c; + wor D; + assign D = 1; + assign D = 0; + assign D = 1; + assign D = 0; + + + wand E; + wire E_wire = E; + + genvar i; + for (i = 0; i < 3; i = i + 1) + begin :genloop + a a_inst ( + .Q(E) + ); + + b b_inst ( + .D(E_wire) + ); + end + +endmodule + |