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author | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:45:54 +0200 |
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committer | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:45:54 +0200 |
commit | f68b658b4b88b9a71377d19d7d693f07eccf433e (patch) | |
tree | 2f382b4db64d9d3d7bbe23740f2a4da7c0152259 | |
parent | c5fe04acfde6e0f8c4c8f3d77a917a5918e8b839 (diff) | |
download | yosys-f68b658b4b88b9a71377d19d7d693f07eccf433e.tar.gz yosys-f68b658b4b88b9a71377d19d7d693f07eccf433e.tar.bz2 yosys-f68b658b4b88b9a71377d19d7d693f07eccf433e.zip |
reformat wand/wor test
-rw-r--r-- | tests/various/wandwor.v | 43 |
1 files changed, 21 insertions, 22 deletions
diff --git a/tests/various/wandwor.v b/tests/various/wandwor.v index d1dca6269..fc072daa3 100644 --- a/tests/various/wandwor.v +++ b/tests/various/wandwor.v @@ -1,34 +1,33 @@ module a(Q); - output wire Q; - - assign Q = 0; + output wire Q = 0; endmodule module b(D); - input wire D; + input wire D; endmodule module c; - wor D; - assign D = 1; - assign D = 0; - assign D = 1; - assign D = 0; + // net definitions + wor D; + wand E; + + // assignments to wired logic nets + assign D = 1; + assign D = 0; + assign D = 1; + assign D = 0; + // assignments of wired logic nets to wires + wire F = E; - wand E; - - genvar i; - for (i = 0; i < 3; i = i + 1) - begin :genloop - a a_inst ( - .Q(E) - ); - - b b_inst ( - .D(E) - ); - end + genvar i; + for (i = 0; i < 3; i = i + 1) + begin : genloop + // connection of module outputs + a a_inst (.Q(E)); + // connection of module inputs + b b_inst (.D(E)); + end endmodule |