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*
Fix check for bad std::regex (fixes #2606)
Michael Singer
2021-03-17
1
-3
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+23
*
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verilog: rebuild user_type_stack from globals before parsing file
Xiretza
2021-03-18
1
-5
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+21
*
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Add simple CI using github actions.
Marcelina Kościelnicka
2021-03-18
1
-0
/
+87
*
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modtools: fix use-after-free of cell pointers in ModWalker
Xiretza
2021-03-18
1
-0
/
+2
*
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quicklogic: PolarPro 3 support
Lofty
2021-03-18
20
-0
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+1033
*
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ast: Use better parameter serialization for paramod names.
Marcelina Kościelnicka
2021-03-18
2
-5
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+28
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Blackbox all whiteboxes after synthesis
gatecat
2021-03-17
16
-9
/
+24
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bugpoint: add runner option
Zachary Snow
2021-03-17
2
-6
/
+20
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sv: carry over global typedefs from previous files
Zachary Snow
2021-03-17
3
-2
/
+65
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verilog: fix buf/not primitives with multiple outputs
Xiretza
2021-03-17
2
-4
/
+30
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blackbox: Include whiteboxed modules
gatecat
2021-03-17
4
-4
/
+19
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Replace assert in get_reference with more useful error message
Lofty
2021-03-17
1
-1
/
+2
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verilog: support module scope identifiers in parametric modules
Zachary Snow
2021-03-16
2
-4
/
+37
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json: Add support for memories.
Marcelina Kościelnicka
2021-03-15
2
-0
/
+88
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proc_arst: Add special-casing of clock signal in conditionals.
Marcelina Kościelnicka
2021-03-15
2
-23
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+82
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opt_clean: Remove init attribute bits together with removed DFFs.
Marcelina Kościelnicka
2021-03-15
2
-11
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+24
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rtlil: Disallow 0-width chunks in SigSpec.
Marcelina Kościelnicka
2021-03-15
2
-18
/
+63
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Merge pull request #2658 from zachjs/parameters-across-files
whitequark
2021-03-14
3
-1
/
+21
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sv: allow globals in one file to depend on globals in another
Zachary Snow
2021-03-12
3
-1
/
+21
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*
Merge pull request #2653 from zachjs/global-parameter
whitequark
2021-03-12
2
-0
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+18
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verilog: disallow overriding global parameters
Zachary Snow
2021-03-11
2
-0
/
+18
*
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Merge pull request #2642 from whitequark/cxxrtl-noproc-fixes
whitequark
2021-03-11
1
-17
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+29
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cxxrtl: don't assert on edge sync rules tied to a constant.
whitequark
2021-03-07
1
-0
/
+4
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*
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cxxrtl: allow `always` sync rules in debug_eval.
whitequark
2021-03-07
1
-17
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+25
*
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Add _pm.h files to GENLIST, fixes vcxsrc target
Miodrag Milanovic
2021-03-11
1
-0
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+9
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*
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Replace assert in xaiger with more useful error message
Dan Ravensloft
2021-03-10
1
-1
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+2
*
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Merge pull request #2643 from zachjs/fix-param-no-default-log
whitequark
2021-03-08
1
-1
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+1
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*
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Fix param without default log line
Zachary Snow
2021-03-07
1
-1
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+1
*
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Bump version
Marcelina Kościelnicka
2021-03-08
1
-1
/
+1
*
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memory_dff: Remove now-useless write port handling.
Marcelina Kościelnicka
2021-03-08
6
-82
/
+19
*
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verilog: Use proc memory writes in the frontend.
Marcelina Kościelnicka
2021-03-08
5
-29
/
+94
*
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Add support for memory writes in processes.
Marcelina Kościelnicka
2021-03-08
16
-43
/
+245
*
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sim: Avoid a crash on empty cell connection.
Marcelina Kościelnicka
2021-03-08
1
-1
/
+1
*
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proc_dff: Fix emitted FF when a register is not assigned in async reset
Marcelina Kościelnicka
2021-03-08
2
-0
/
+27
*
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memory_dff: Remove code looking for $mux cells.
Marcelina Kościelnicka
2021-03-08
1
-56
/
+12
*
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tests/bram: Do not generate write address collisions.
Marcelina Kościelnicka
2021-03-08
1
-5
/
+23
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/
*
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Replace assert in abc9_ops with more useful error message
Dan Ravensloft
2021-03-07
1
-1
/
+9
*
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Merge pull request #2626 from zachjs/param-no-default
whitequark
2021-03-07
12
-5
/
+225
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*
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sv: support for parameters without default values
Zachary Snow
2021-03-02
12
-5
/
+225
*
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Merge pull request #2632 from zachjs/width-limit
whitequark
2021-03-07
3
-0
/
+39
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*
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verilog: impose limit on maximum expression width
Zachary Snow
2021-03-04
3
-0
/
+39
*
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sv: fix some edge cases for unbased unsized literals
Zachary Snow
2021-03-06
4
-1
/
+70
*
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proc_clean: Fix empty case removal conditions.
Marcelina Kościelnicka
2021-03-06
1
-10
/
+21
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Remove a few functions that, in fact, did not exist in the first place.
Marcelina Kościelnicka
2021-03-06
2
-3
/
+1
*
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Replace assert in addModule with more useful error message
Dan Ravensloft
2021-03-06
1
-1
/
+2
*
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Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addr
whitequark
2021-03-05
1
-1
/
+3
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cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
whitequark
2021-03-05
1
-1
/
+3
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/
*
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Merge pull request #2634 from whitequark/cxxrtl-debug-wire-types
whitequark
2021-03-05
1
-0
/
+46
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*
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cxxrtl: add pass debug flag to show assigned wire types.
whitequark
2021-03-05
1
-0
/
+46
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/
/
*
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Merge pull request #2633 from whitequark/cxxrtl-no-top
whitequark
2021-03-05
1
-1
/
+1
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