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| author | gatecat <gatecat@ds0.me> | 2021-03-17 12:06:09 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-03-17 13:58:04 +0000 |
| commit | dd6d34f461910a120ac95c485fe34cca6485b95e (patch) | |
| tree | 262dd91cfc969b492b99ce8fa7e3c94fd5d412be | |
| parent | 937392ad337c4f70569535e83f7016245addb2c7 (diff) | |
| download | yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.tar.gz yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.tar.bz2 yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.zip | |
blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
| -rw-r--r-- | kernel/rtlil.cc | 4 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 | ||||
| -rw-r--r-- | passes/cmds/blackbox.cc | 3 | ||||
| -rw-r--r-- | tests/various/blackbox_wb.ys | 14 |
4 files changed, 19 insertions, 4 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32069ce03..87cbaa0d5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -808,12 +808,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const return result; } -std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const +std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const { std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (it.second->get_blackbox_attribute()) + if (it.second->get_blackbox_attribute(include_wb)) continue; else if (selected_whole_module(it.first)) result.push_back(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a747b9d3c..bbdf355fa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1112,7 +1112,7 @@ struct RTLIL::Design std::vector<RTLIL::Module*> selected_modules() const; std::vector<RTLIL::Module*> selected_whole_modules() const; - std::vector<RTLIL::Module*> selected_whole_modules_warn() const; + std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const; #ifdef WITH_PYTHON static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void); #endif diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index 08a635514..fca91852c 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -46,10 +46,11 @@ struct BlackboxPass : public Pass { } extra_args(args, argidx, design); - for (auto module : design->selected_whole_modules_warn()) + for (auto module : design->selected_whole_modules_warn(true)) { module->makeblackbox(); module->set_bool_attribute(ID::blackbox); + module->set_bool_attribute(ID::whitebox, false); } } } BlackboxPass; diff --git a/tests/various/blackbox_wb.ys b/tests/various/blackbox_wb.ys new file mode 100644 index 000000000..f9c9bec06 --- /dev/null +++ b/tests/various/blackbox_wb.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT +(* whitebox *) +module box(input a, output q); +assign q = ~a; +endmodule + +module top(input a, output q); +box box_i(.a(a), .q(q)); +endmodule +EOT +select -assert-count 1 =box/t:$not +blackbox =box +select -assert-count 0 =A:whitebox +select -assert-count 0 =box/t:$not |