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author | Zachary Snow <zach@zachjs.com> | 2021-03-16 11:06:40 -0400 |
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committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-17 15:53:52 -0400 |
commit | f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e (patch) | |
tree | 4edd598b167d6422f64743b30587ead247346e46 | |
parent | 092e923330ce23adffa7843a27bdba8a0b139e58 (diff) | |
download | yosys-f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e.tar.gz yosys-f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e.tar.bz2 yosys-f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e.zip |
sv: carry over global typedefs from previous files
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 7 | ||||
-rw-r--r-- | tests/verilog/typedef_across_files.ys | 23 | ||||
-rw-r--r-- | tests/verilog/typedef_legacy_conflict.ys | 37 |
3 files changed, 65 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index e2aecd99b..5907707c8 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -61,8 +61,11 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std } } } - user_type_stack.clear(); - user_type_stack.push_back(new UserTypeMap()); + + // carry over typedefs from previous files, but allow them to be overridden + // note that these type maps are currently never reclaimed + if (user_type_stack.empty() || !user_type_stack.back()->empty()) + user_type_stack.push_back(new UserTypeMap()); } struct VerilogFrontend : public Frontend { diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys new file mode 100644 index 000000000..ca9bba736 --- /dev/null +++ b/tests/verilog/typedef_across_files.ys @@ -0,0 +1,23 @@ +read_verilog -sv <<EOF +typedef logic T; +EOF + +read_verilog -sv <<EOF +typedef T [3:0] S; +EOF + +read_verilog -sv <<EOF +module top; + T t; + S s; + always @* begin + assert ($bits(t) == 1); + assert ($bits(s) == 4); + end +endmodule +EOF + +proc +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys new file mode 100644 index 000000000..8dff4ec5f --- /dev/null +++ b/tests/verilog/typedef_legacy_conflict.ys @@ -0,0 +1,37 @@ +read_verilog -sv <<EOF +typedef logic T; +typedef T [3:0] S; +EOF + +read_verilog -sv <<EOF +module example; + // S and T refer to the definitions from the first file + T t; + S s; + always @* begin + assert ($bits(t) == 1); + assert ($bits(s) == 4); + end +endmodule + +typedef byte T; +typedef T S; + +module top; + // S and T refer to the most recent overrides + T t; + S s; + always @* begin + assert ($bits(t) == 8); + assert ($bits(s) == 8); + end + example e(); +endmodule +EOF + +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all |