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| author | whitequark <whitequark@whitequark.org> | 2021-03-05 12:08:48 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-03-05 12:09:02 +0000 |
| commit | 14ce8bdaa6a1120c48a934697488c463ffb15b48 (patch) | |
| tree | c80fb0340ae8350a42acadd21bb16ce6e65170ba | |
| parent | 7d2097b00538fa366cc433b23c2c307db0e3a4be (diff) | |
| download | yosys-14ce8bdaa6a1120c48a934697488c463ffb15b48.tar.gz yosys-14ce8bdaa6a1120c48a934697488c463ffb15b48.tar.bz2 yosys-14ce8bdaa6a1120c48a934697488c463ffb15b48.zip | |
cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 39046bd78..f2ff8a468 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1231,7 +1231,9 @@ struct CxxrtlWorker { RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; std::string valid_index_temp = fresh_temporary(); f << indent << "auto " << valid_index_temp << " = memory_index("; - dump_sigspec_rhs(cell->getPort(ID::ADDR)); + // Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous + // memory read ports can. + dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug); f << ", " << memory->start_offset << ", " << memory->size << ");\n"; if (cell->type == ID($memrd)) { bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones(); |