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* | Merge pull request #405 from azonenberg/gpak-refactoringClifford Wolf2017-09-025-137/+157
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| * Fixed typo in error messageAndrew Zonenberg2017-09-011-1/+1
| * Added blackbox $__COUNT_ cell modelAndrew Zonenberg2017-09-012-0/+18
| * Refactoring: moved modules still in cells_sim to cells_sim_wipAndrew Zonenberg2017-09-013-136/+138
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-09-015-77/+214
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| * Merge pull request #399 from azonenberg/counter-extractionClifford Wolf2017-08-315-77/+214
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| | * Merge branch 'counter-extraction' of github.com:azonenberg/yosys into counter...Andrew Zonenberg2017-08-303-34/+54
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| | | * Merge branch 'master' of https://github.com/cliffordwolf/yosys into counter-e...Andrew Zonenberg2017-08-303-34/+54
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| | * | extract_counter: Added optimizations to remove unused high-order bitsAndrew Zonenberg2017-08-301-16/+34
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| | * extract_counter: Minor changes requested to comply with upstream policy, fixe...Andrew Zonenberg2017-08-303-7/+8
| | * Finished refactoring counter extraction to be nice and generic. Implemented t...Andrew Zonenberg2017-08-283-12/+94
| | * Refactored extract_counter to be generic vs GreenPAK specificAndrew Zonenberg2017-08-281-51/+87
| | * Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to ...Andrew Zonenberg2017-08-284-13/+13
* | | Merge branch 'ChipScan-master'Clifford Wolf2017-09-016-59/+76
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| * | | Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-012-5/+5
| * | | updated to use get_src_attribute() and set_src_attribute().Jason Lowdermilk2017-08-313-10/+7
| * | | Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-303-34/+54
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| | * | Merge pull request #397 from azonenberg/gpak-libfixesClifford Wolf2017-08-301-34/+34
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| | * | Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-e...Andrew Zonenberg2017-08-281-34/+34
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* | / Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-302-0/+20
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| * fix indent levelJason Lowdermilk2017-08-301-2/+2
| * Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-295-25/+45
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* Merge branch 'azonenberg-recover-reduce'Clifford Wolf2017-08-282-0/+240
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| * Rename recover_reduce to extract_reduce, fix args handlingClifford Wolf2017-08-282-8/+25
| * Merge branch 'recover-reduce' of https://github.com/azonenberg/yosys into azo...Clifford Wolf2017-08-282-0/+223
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| * recover_reduce: Update documentationRobert Ou2017-08-271-8/+11
| * recover_reduce: Reindent using tabsRobert Ou2017-08-271-190/+190
| * recover_reduce: Rename recover_reduce_core to recover_reduceRobert Ou2017-08-273-101/+0
| * recover_reduce: Add driver script for the $reduce_* recover featureRobert Ou2017-08-272-0/+101
| * recover_reduce_core: Finish implementing the core functionRobert Ou2017-08-271-0/+110
| * recover_reduce_core: Initial commitRobert Ou2017-08-272-0/+110
* | Further improve extract_fa passClifford Wolf2017-08-281-1/+42
* | Merge pull request #392 from azonenberg/greenpak-portfixesClifford Wolf2017-08-281-2/+2
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| * Fixed bug causing GP_SPI model to not synthesizeAndrew Zonenberg2017-08-271-2/+2
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* Don't track , ... contradictions through x/z-bitsClifford Wolf2017-08-251-1/+4
* Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_exprClifford Wolf2017-08-251-0/+72
* Merge branch 'extract_fa'Clifford Wolf2017-08-252-0/+502
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| * Further improve extract_fa (seems to be fully functional now)Clifford Wolf2017-08-251-10/+226
| * Rename "adders" to "extract_fa"Clifford Wolf2017-08-252-28/+16
| * Towards more generic "adder" function extractorClifford Wolf2017-08-231-202/+53
| * Add experimental adders passClifford Wolf2017-08-222-0/+447
* | Fix bug in write_smt2 (export logic driving hierarchical cells before exporti...Clifford Wolf2017-08-251-34/+34
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* Add hashlib support for hashing of poolsClifford Wolf2017-08-221-0/+7
* Add consteval support for $_ANDNOT_ and $_ORNOT_Clifford Wolf2017-08-221-0/+4
* Remove some dead code from fsm_mapClifford Wolf2017-08-211-3/+0
* Rename "singleton" pass to "uniquify"Clifford Wolf2017-08-203-21/+22
* More intuitive handling of "cd .." for singleton modulesClifford Wolf2017-08-191-2/+38
* Add "sim -zinit -rstlen"Clifford Wolf2017-08-181-1/+53
* Merge branch 'sim'Clifford Wolf2017-08-184-0/+848
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| * Add "sim" support for memoriesClifford Wolf2017-08-181-2/+136
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