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authorAndrew Zonenberg <azonenberg@drawersteak.com>2017-08-30 18:16:15 -0700
committerAndrew Zonenberg <azonenberg@drawersteak.com>2017-08-30 18:16:15 -0700
commit16043b79b6c42b1d25604ed40221a5479e8811c0 (patch)
tree9bd2839064c2e2a9d6b6c9de71918918c3b65ee0
parented1e3ed39bf15ff9276587325920a329321bdac2 (diff)
parent06754108fc3cc3d78e7b86d7093da110cc716224 (diff)
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Merge branch 'counter-extraction' of github.com:azonenberg/yosys into counter-extraction
-rw-r--r--kernel/rtlil.cc16
-rw-r--r--kernel/rtlil.h4
-rw-r--r--techlibs/greenpak4/cells_sim_digital.v68
3 files changed, 54 insertions, 34 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 4427303cc..f3522e30b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -234,6 +234,22 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
return data;
}
+void RTLIL::AttrObject::set_src_attribute(const std::string &src)
+{
+ if (src.empty())
+ attributes.erase("\\src");
+ else
+ attributes["\\src"] = src;
+}
+
+std::string RTLIL::AttrObject::get_src_attribute() const
+{
+ std::string src;
+ if (attributes.count("\\src"))
+ src = attributes.at("\\src").decode_string();
+ return src;
+}
+
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index be558932f..31f7f9d31 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -505,9 +505,13 @@ struct RTLIL::AttrObject
void set_bool_attribute(RTLIL::IdString id);
bool get_bool_attribute(RTLIL::IdString id) const;
+
void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
pool<string> get_strpool_attribute(RTLIL::IdString id) const;
+
+ void set_src_attribute(const std::string &src);
+ std::string get_src_attribute() const;
};
struct RTLIL::SigChunk
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 043cd18d4..b87795ceb 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
- if(KEEP) begin
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
//Resets
- if(RST) begin
+ if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
- end
- end
-
- "FALLING": begin
- always @(posedge CLK, negedge RST) begin
-
- if(KEEP) begin
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
- //Resets
- if(!RST) begin
- if(RESET_VALUE == "ZERO")
- count <= 0;
- else
- count <= COUNT_TO;
- end
-
end
end
@@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
//Main counter
- if(KEEP) begin
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
//Resets
- if(RST) begin
+ if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
- end
- end
-
- "FALLING": begin
- always @(posedge CLK, negedge RST) begin
-
//Main counter
- if(KEEP) begin
+ else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end
- //Resets
- if(!RST) begin
- if(RESET_VALUE == "ZERO")
- count <= 0;
- else
- count <= COUNT_TO;
- end
-
end
end