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| author | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
|---|---|---|
| committer | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
| commit | 8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a (patch) | |
| tree | aa6377e3fd95214735bca3b6c3fe920b78e29f08 | |
| parent | 71d43cfc08b1949d5d07d6715107cd87c40e4465 (diff) | |
| download | yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.gz yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.bz2 yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.zip | |
updated to use get_src_attribute() and set_src_attribute().
| -rw-r--r-- | passes/techmap/alumacc.cc | 7 | ||||
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 6 |
3 files changed, 7 insertions, 10 deletions
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 9593ef27a..920448915 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -352,13 +352,12 @@ struct AlumaccWorker { auto n = it.second; auto cell = module->addCell(NEW_ID, "$macc"); - auto src = n->cell->attributes["\\src"].decode_string(); macc_counter++; log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell)); - if (!src.empty()) cell->attributes["\\src"] = src; + cell->set_src_attribute(n->cell->get_src_attribute()); n->macc.optimize(GetSize(n->y)); n->macc.to_cell(cell); @@ -480,8 +479,8 @@ struct AlumaccWorker log("%s%s", i ? ", ": "", log_id(n->cells[i])); log(": %s\n", log_id(n->alu_cell)); - src = n->cells.size() > 0 ? n->cells[0]->attributes["\\src"].decode_string() : ""; - if (!src.empty()) n->alu_cell->attributes["\\src"] = src; + if (n->cells.size() > 0) + n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute()); n->alu_cell->setPort("\\A", n->a); n->alu_cell->setPort("\\B", n->b); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 71d708c18..4cb1489a8 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -478,14 +478,14 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare auto cell_type = cell->type; auto cell_name = cell->name; auto cell_connections = cell->connections(); - std::string src = cell->attributes["\\src"].decode_string(); + std::string src = cell->get_src_attribute(); module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name); - if (!src.empty()) new_cell->attributes["\\src"] = src; + new_cell->set_src_attribute(src); bool has_q = false, has_qn = false; for (auto &port : cm.ports) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index acc5d7471..d9e81e808 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -172,7 +172,6 @@ struct TechmapWorker std::string orig_cell_name; pool<string> extra_src_attrs; - std::string src = cell->attributes["\\src"].decode_string(); if (!flatten_mode) { @@ -341,7 +340,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, it.second); design->select(module, c); - if (!src.empty()) c->attributes["\\src"] = src; + c->set_src_attribute(cell->get_src_attribute()); if (!flatten_mode && c->type.substr(0, 2) == "\\$") c->type = c->type.substr(1); @@ -467,7 +466,6 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - std::string src = cell->attributes["\\src"].decode_string(); std::string cell_type = cell->type.str(); if (in_recursion && cell_type.substr(0, 2) == "\\$") @@ -517,7 +515,7 @@ struct TechmapWorker extmapper_module = extmapper_design->addModule(m_name); RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - if (!src.empty()) extmapper_cell->attributes["\\src"] = src; + extmapper_cell->set_src_attribute(cell->get_src_attribute()); int port_counter = 1; for (auto &c : extmapper_cell->connections_) { |