Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Make it work on all | Miodrag Milanovic | 2021-11-05 | 2 | -5/+5 |
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* | Correct way of setting maybe_unsused on labels | Miodrag Milanovic | 2021-11-05 | 1 | -4/+2 |
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* | Add missing changelog item | Miodrag Milanovic | 2021-11-05 | 1 | -0/+1 |
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* | Update command reference | Miodrag Milanovic | 2021-11-05 | 1 | -0/+17 |
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* | Merge pull request #3067 from YosysHQ/aki/ci_update | Miodrag Milanović | 2021-11-05 | 4 | -101/+293 |
|\ | | | | | Update the Linux and macOS CI jobs | ||||
| * | ci: removed the old `test.yml` workflow, as it was replaced by ↵ | Aki Van Ness | 2021-10-31 | 1 | -91/+0 |
| | | | | | | | | `test-linux.yml` and `test-macos.yml` | ||||
| * | ci: expanded the macOS tests suite to cover more compilers and C++ versions | Aki Van Ness | 2021-10-31 | 1 | -0/+157 |
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| * | ci: expanded the Linux test suite to cover more compilers and C++ versions | Aki Van Ness | 2021-10-31 | 1 | -0/+125 |
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| * | Changed the Makefile to have an explicit `CXXSTD` parameter which allows for ↵ | Aki Van Ness | 2021-10-31 | 1 | -10/+11 |
| | | | | | | | | the setting of other C++ standards, the default is `c++11` | ||||
* | | Removed semicolon from macro | Miodrag Milanovic | 2021-11-05 | 1 | -1/+1 |
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* | | Bump version | github-actions[bot] | 2021-11-03 | 1 | -1/+1 |
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* | | flatten: Keep sigmap around between flatten_cell invocations. | Marcelina Kościelnicka | 2021-11-02 | 1 | -3/+4 |
| | | | | | | | | Fixes #3064. | ||||
* | | Bump version | github-actions[bot] | 2021-11-02 | 1 | -1/+1 |
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* | | Merge pull request #3068 from YosysHQ/claire/verific_cfg | Claire Xen | 2021-11-01 | 1 | -2/+75 |
|\ \ | | | | | | | Add "verific -cfg" command | ||||
| * | | Add "verific -cfg" command | Claire Xenia Wolf | 2021-11-01 | 1 | -2/+75 |
|/ / | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* / | Bump version | github-actions[bot] | 2021-11-01 | 1 | -1/+1 |
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* | Merge pull request #3066 from YosysHQ/claire/verific_gclk | Claire Xen | 2021-10-31 | 1 | -12/+67 |
|\ | | | | | Fix verific gclk handling for async-load FFs | ||||
| * | Fix verific gclk handling for async-load FFs | Claire Xenia Wolf | 2021-10-31 | 1 | -12/+67 |
|/ | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | Bump version | github-actions[bot] | 2021-10-30 | 1 | -1/+1 |
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* | Add missing items in CHANGELOG | Miodrag Milanovic | 2021-10-29 | 1 | -0/+6 |
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* | Update command reference part of manual | Miodrag Milanovic | 2021-10-29 | 1 | -340/+1444 |
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* | Bump version | github-actions[bot] | 2021-10-28 | 1 | -1/+1 |
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* | Merge pull request #3063 from YosysHQ/micko/verific_aldff | Miodrag Milanović | 2021-10-27 | 2 | -8/+1 |
|\ | | | | | Enable async load dff emit by default in Verific | ||||
| * | Enable async load dff emit by default in Verific | Miodrag Milanovic | 2021-10-27 | 1 | -1/+1 |
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| * | Revert "Compile option for enabling async load verific support" | Miodrag Milanovic | 2021-10-27 | 2 | -8/+1 |
| | | | | | | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467. | ||||
* | | ecp5: Add support for mapping aldff. | Marcelina Kościelnicka | 2021-10-27 | 2 | -13/+13 |
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* | proc_dff: Emit $aldff. | Marcelina Kościelnicka | 2021-10-27 | 1 | -32/+7 |
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* | dfflegalize: Add tests for aldff lowering. | Marcelina Kościelnicka | 2021-10-27 | 2 | -0/+240 |
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* | dfflegalize: Add tests targetting aldff. | Marcelina Kościelnicka | 2021-10-27 | 7 | -7/+320 |
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* | dfflegalize: Refactor, add aldff support. | Marcelina Kościelnicka | 2021-10-27 | 12 | -1053/+1137 |
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* | Bump version | github-actions[bot] | 2021-10-27 | 1 | -1/+1 |
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* | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 15 | -42/+397 |
| | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change | ||||
* | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 5 | -28/+61 |
| | | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version. | ||||
* | Bump version | github-actions[bot] | 2021-10-26 | 1 | -1/+1 |
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* | Compile option for enabling async load verific support | Miodrag Milanovic | 2021-10-25 | 2 | -1/+8 |
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* | Bump version | github-actions[bot] | 2021-10-22 | 1 | -1/+1 |
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* | Change implicit conversions from bool to Sig* to explicit. | Marcelina Kościelnicka | 2021-10-21 | 2 | -6/+8 |
| | | | | Also fixes some completely broken code in extract_reduce. | ||||
* | Merge pull request #3057 from YosysHQ/claire/verific_latches | Claire Xen | 2021-10-21 | 1 | -4/+61 |
|\ | | | | | Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} | ||||
| * | Fix verific.cc PRIM_DLATCH handling | Claire Xenia Wolf | 2021-10-21 | 1 | -1/+7 |
| | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} | Claire Xenia Wolf | 2021-10-21 | 1 | -4/+55 |
|/ | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | extract_reduce: Refactor and fix input signal construction. | Marcelina Kościelnicka | 2021-10-21 | 2 | -63/+46 |
| | | | | Fixes #3047. | ||||
* | Bump version | github-actions[bot] | 2021-10-21 | 1 | -1/+1 |
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* | If verific have vhdl lib it is required by other libs | Miodrag Milanovic | 2021-10-20 | 1 | -0/+4 |
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* | Forgot to remove from main list | Miodrag Milanovic | 2021-10-20 | 1 | -1/+1 |
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* | Option to disable verific VHDL support | Miodrag Milanovic | 2021-10-20 | 3 | -11/+50 |
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* | Bump version | github-actions[bot] | 2021-10-20 | 1 | -1/+1 |
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* | Fixed Verific parser error in ice40 cell library | Claire Xenia Wolf | 2021-10-19 | 1 | -22/+62 |
| | | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode | ||||
* | Merge pull request #3045 from galibert/master | Miodrag Milanović | 2021-10-19 | 1 | -0/+18 |
|\ | | | | | CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose | ||||
| * | CycloneV: Add (passthrough) support for cyclonev_oscillator | Olivier Galibert | 2021-10-17 | 1 | -1/+11 |
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| * | CycloneV: Add (passthrough) support for ↵ | Olivier Galibert | 2021-10-17 | 1 | -0/+8 |
| | | | | | | | | cyclonev_hps_interface_mpu_general_purpose |