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* Add hashlib support for hashing of poolsClifford Wolf2017-08-221-0/+7
* Add consteval support for $_ANDNOT_ and $_ORNOT_Clifford Wolf2017-08-221-0/+4
* Remove some dead code from fsm_mapClifford Wolf2017-08-211-3/+0
* Rename "singleton" pass to "uniquify"Clifford Wolf2017-08-203-21/+22
* More intuitive handling of "cd .." for singleton modulesClifford Wolf2017-08-191-2/+38
* Add "sim -zinit -rstlen"Clifford Wolf2017-08-181-1/+53
* Merge branch 'sim'Clifford Wolf2017-08-184-0/+848
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| * Add "sim" support for memoriesClifford Wolf2017-08-181-2/+136
| * Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-182-0/+37
| * Add support for assert/assume/cover to "sim" commandClifford Wolf2017-08-181-4/+47
| * Add writeback mode to "sim" commandClifford Wolf2017-08-171-0/+44
| * Improve "sim" commandClifford Wolf2017-08-171-54/+272
| * Add "sim" command skeletonClifford Wolf2017-08-162-0/+372
* | Merge pull request #386 from azonenberg/gpak-countersClifford Wolf2017-08-161-73/+82
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| * Fixed more issues with GreenPAK counter sim modelsAndrew Zonenberg2017-08-151-19/+23
| * Updated PGEN model to have level triggered reset (matches actual hardware beh...Andrew Zonenberg2017-08-151-4/+4
| * Fixed bug in GP_COUNTx modelAndrew Zonenberg2017-08-151-7/+12
| * Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was highAndrew Zonenberg2017-08-151-47/+47
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* Merge branch 'azonenberg-rmports'Clifford Wolf2017-08-152-0/+188
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| * Mostly coding style related fixes in rmports passClifford Wolf2017-08-151-30/+33
| * Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg...Clifford Wolf2017-08-152-0/+185
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| * rmports: Now remove ports from cell instances if we optimized them out of tha...Andrew Zonenberg2017-08-141-2/+35
| * ProcessModule is no longer virtual (why was it in the first place?)Andrew Zonenberg2017-08-141-1/+1
| * rmports now works on all modules in the design, not just the top.Andrew Zonenberg2017-08-141-4/+7
| * Updated Makefile to reflect opt_rmports being renamed to rmportsAndrew Zonenberg2017-08-141-1/+1
| * Renamed opt_rmports pass to rmportsAndrew Zonenberg2017-08-141-5/+5
| * Improved handling of constant connections in opt_rmportsAndrew Zonenberg2017-08-141-0/+2
| * Fixed handling of cell ports that aren't wiresAndrew Zonenberg2017-08-141-0/+3
| * opt_rmports: Fixed incorrect handling of multi-bit netsAndrew Zonenberg2017-08-141-12/+27
| * Removed commented out debug codeAndrew Zonenberg2017-08-141-4/+0
| * Added opt_rmports pass (remove unconnected ports from top-level modules)Andrew Zonenberg2017-08-142-0/+133
* | Merge pull request #381 from azonenberg/countfixClifford Wolf2017-08-144-504/+900
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| * | Fixed typo in GP_COUNT8 sim modelAndrew Zonenberg2017-08-141-1/+1
| * | Fixed typo in error messageAndrew Zonenberg2017-08-141-1/+1
| * | Changed LEVEL resets for GP_COUNTx to be properly synthesizeableAndrew Zonenberg2017-08-141-48/+60
| * | Changed LEVEL resets to be edge triggered anywayAndrew Zonenberg2017-08-141-4/+4
| * | Added level-triggered reset support to GP_COUNTx simulation modelsAndrew Zonenberg2017-08-141-2/+68
| * | Fixed undeclared "count" in GP_COUNT8_ADVAndrew Zonenberg2017-08-141-0/+2
| * | Fixed undeclared "count" in GP_COUNT14_ADVAndrew Zonenberg2017-08-141-0/+2
| * | Fixed typo in last commitAndrew Zonenberg2017-08-141-3/+3
| * | Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock di...Andrew Zonenberg2017-08-142-37/+293
| * | Fixed typo in COUNT8 modelAndrew Zonenberg2017-08-141-2/+2
| * | Moved GP_POR out of digital cells b/c it has delaysAndrew Zonenberg2017-08-142-21/+21
| * | Improved cells_sim_digital model for GP_COUNT8Andrew Zonenberg2017-08-142-40/+75
| * | Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digitalAndrew Zonenberg2017-08-144-428/+451
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* | Merge pull request #383 from azonenberg/abcfnamesClifford Wolf2017-08-141-0/+3
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| * | abc: Allow +/ filenames in the abc commandRobert Ou2017-08-141-0/+3
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* | Merge pull request #382 from azonenberg/jsoniofixClifford Wolf2017-08-141-0/+1
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| * | json: Parse inout correctly rather than as an outputRobert Ou2017-08-141-0/+1
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* | Merge pull request #384 from azonenberg/crtechlibClifford Wolf2017-08-141-2/+66
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