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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 20:21:18 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:39 -0700 |
| commit | db20e3f1c2926d18df5db759341b46a76299607b (patch) | |
| tree | 3d32584643e486df31cc98d89bf59f9f30d8c2e8 | |
| parent | 3618ca22181715cd24f6dca5911019d406f562e7 (diff) | |
| download | yosys-db20e3f1c2926d18df5db759341b46a76299607b.tar.gz yosys-db20e3f1c2926d18df5db759341b46a76299607b.tar.bz2 yosys-db20e3f1c2926d18df5db759341b46a76299607b.zip | |
Fixed undeclared "count" in GP_COUNT14_ADV
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 250f1da6a..0ed40f79c 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -116,6 +116,8 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, end end + reg[13:0] count = COUNT_TO; + //Combinatorially output underflow flag whenever we wrap low always @(*) begin if(UP) |