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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 20:46:00 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:40 -0700 |
| commit | c205d571df90b7bdca5207e441dec5e1dabdc2ed (patch) | |
| tree | d9cf66130420a00a69ab3a886648ff0247d4e89d | |
| parent | 0a6c702c41154e15046ea9bcc1568e5250da7299 (diff) | |
| download | yosys-c205d571df90b7bdca5207e441dec5e1dabdc2ed.tar.gz yosys-c205d571df90b7bdca5207e441dec5e1dabdc2ed.tar.bz2 yosys-c205d571df90b7bdca5207e441dec5e1dabdc2ed.zip | |
Fixed typo in error message
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 30fbef9f2..cda83862a 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -80,7 +80,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); "BOTH": begin initial begin - $display("Both-edge reset mode for GP_COUNT8 not implemented"); + $display("Both-edge reset mode for GP_COUNT14 not implemented"); $finish; end end |