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* verific: do not assert if wire not found; warn insteadEddie Hung2020-04-232-2/+7
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* Merge pull request #1974 from YosysHQ/eddie/abc9_disable_mfsEddie Hung2020-04-231-2/+17
|\ | | | | abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
| * abc9: tolerate ABC nonzero exit code if output.aig; write before &mfsEddie Hung2020-04-203-6/+13
| | | | | | | | | | Re-enable mfs for xilinx/ecp5 speculatively -- if it fails, use pre-mfs result
| * xilinx/ecp5: disable abc9's "&mfs" optimisationEddie Hung2020-04-203-0/+8
| | | | | | | | Can sometimes fire an assertion, e.g. #1962
* | Merge pull request #1989 from boqwxp/qbfsat_anyconst_sourcelocsClaire Wolf2020-04-231-5/+2
|\ \ | | | | | | qbfsat: Make hole name recovery from source locations more robust.
| * | qbfsat: Make hole name recovery more robust. Allow multiple cell types to ↵Alberto Gonzalez2020-04-231-5/+2
| | | | | | | | | | | | share the same source location as long as only one `$anyconst` or `$anyseq` has that location.
* | | Merge pull request #1988 from boqwxp/qbfsatClaire Wolf2020-04-231-6/+22
|\ \ \ | | | | | | | | qbfsat: Add `-assume-negative-polarity` option.
| * | | qbfsat: Add `-assume-negative-polarity` option.Alberto Gonzalez2020-04-231-6/+22
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* | | Merge pull request #1986 from YosysHQ/eddie/verific_enumClaire Wolf2020-04-231-0/+20
|\ \ \ | | | | | | | | verific: import enum attributes from verific
| * | | verific: import enum attributes from verificEddie Hung2020-04-221-0/+20
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* | | | intel_alm: work around a Quartus ICEDan Ravensloft2020-04-232-0/+22
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* | | | Merge pull request #1984 from YosysHQ/eddie/getParam_exceptionEddie Hung2020-04-227-21/+34
|\ \ \ \ | |_|/ / |/| | | kernel: Cell::getParam() to throw exception again if not found
| * | | ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
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| * | | tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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| * | | xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 onlyEddie Hung2020-04-221-1/+1
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| * | | test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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| * | | xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
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| * | | xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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| * | | kernel: Cell::getParam() to throw exception again if not foundEddie Hung2020-04-221-3/+2
|/ / / | | | | | | | | | As it did before #1945
* | | Merge pull request #1949 from YosysHQ/eddie/select_blackboxEddie Hung2020-04-222-9/+54
|\ \ \ | |/ / |/| | select: do not select inside black-/white- boxes unless '=' prefix used
| * | Update passes/cmds/select.ccClaire Wolf2020-04-221-2/+2
| | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | tests: update select black/white-box testsEddie Hung2020-04-221-0/+7
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| * | select: do not select black/white boxes by default, '=' prefix to do soEddie Hung2020-04-221-5/+5
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| * | Add '=' selection pattern prefix for non-blackbox only patternsClaire Wolf2020-04-211-12/+26
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | select: add test for not selecting inside black/white boxesEddie Hung2020-04-161-0/+21
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| * | select: do not select inside blackboxesEddie Hung2020-04-161-0/+3
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* | | Merge pull request #1983 from YosysHQ/eddie/use_default_paramEddie Hung2020-04-229-60/+54
|\ \ \ | | | | | | | | Cleanup use of hard-coded default parameters in light of #1945
| * | | Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-229-60/+54
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* | | | Merge pull request #1982 from AsuMagic/asu/cxxrtl-memory-queue-optwhitequark2020-04-221-3/+5
|\ \ \ \ | | | | | | | | | | cxxrtl: keep the memory write queue sorted on insertion.
| * | | | cxxrtl: keep the memory write queue sorted on insertion.Asu2020-04-221-3/+5
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Strategically inserting the pending memory write in memory::update to keep the queue sorted allows us to skip the queue sort in memory::commit. The Minerva SRAM SoC runs ~7% faster as a result.
* | | | Merge pull request #1969 from boqwxp/pool_emplaceEddie Hung2020-04-221-2/+32
|\ \ \ \ | |/ / / |/| | | kernel: Add `pool` support for rvalue references and C++11 move semantics.
| * | | pool: add emplace() functionEddie Hung2020-04-221-0/+6
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| * | | kernel: Rename arguments to rvalue-reference-accepting functions.Alberto Gonzalez2020-04-211-8/+8
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| * | | Add rvalue-reference-accepting `entry_t` constructor for `pool`.Alberto Gonzalez2020-04-201-0/+1
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| * | | In `pool`, construct `entry_t`s in-place and add an ↵Alberto Gonzalez2020-04-201-2/+25
| | | | | | | | | | | | | | | | rvalue-accepting-and-forwarding `insert()` method.
* | | | Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-222-2/+4
|\ \ \ \ | | | | | | | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share
| * | | | yosys-config: spellingEddie Hung2020-04-221-1/+1
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| * | | | tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
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* | | | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-223-7/+30
|\ \ \ \ | | | | | | | | | | design: -import to not count black/white-boxes as candidates for top
| * | | | design: add testEddie Hung2020-04-162-5/+22
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| * | | | design: -import to not count black/white-boxes as candidates for topEddie Hung2020-04-161-2/+8
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* | | | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-222-1/+18
|\ \ \ \ | | | | | | | | | | sim: Fix handling of constant-connected cell inputs at startup
| * | | | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-212-1/+18
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Merge pull request #1979 from whitequark/cxxrtl-go-fasterClaire Wolf2020-04-222-184/+396
|\ \ \ \ \ | | | | | | | | | | | | cxxrtl: Gas gas gas! I'm gonna step on the gas! Tonight I'll fly!
| * | | | | cxxrtl: run edge detectors only once in eval().whitequark2020-04-221-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | As a result, Minerva SRAM SoC runs ~15% faster.
| * | | | | cxxrtl: add an unsupported knob for manipulating clock trees.whitequark2020-04-221-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is quite possibly the worst way to implement this, but it does work for a subset of well-behaved designs, and can be used to measure how much performance is lost simulating the inactive edge of a clock. It should be replaced with a clock tree analyzer generating safe code once it is clear how should such a thing look like.
| * | | | | cxxrtl: use log_id() where appropriate. NFC.whitequark2020-04-211-4/+4
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| * | | | | cxxrtl: add (*cxxrtl.{comb,sync}*) annotations on black box outputs.whitequark2020-04-211-65/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the annotations are not used, this commit does not alter semantics at all, other than removing elision of outputs of black box cells. (Elision of such outputs is expected to be too rare to have any noticeable benefit, and the implementation was somewhat of a hack.) The (* cxxrtl.comb *) annotation alters the semantics of the output of the black box it is applied to such that, if the black box converges immediately, no additional delta cycle is necessary to propagate the computed combinatorial value upwards in hierarchy. The (* cxxrtl.sync *) annotation alters the semantics of the output of the black box it is applied to such as to remove any uses of the black box by the wires connected to this output, and break false feedback arcs arising from conservative modeling of dependencies of the black box. Although currently these attributes are only recognized on black boxes, if separate compilation is added in the future, it could also emit and consume them.
| * | | | | cxxrtl: s/sync_{wire,type}/edge_{wire,type}/. NFC.whitequark2020-04-211-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The attribute for this is called (* cxxrtl.edge *), and there is a planned attribute (* cxxrtl.sync *) that would cause blackbox cell outputs to be added to sync defs rather than comb defs. Rename the edge detector related stuff to avoid confusion.
| * | | | | cxxrtl: use one delta cycle for immediately converging netlists.whitequark2020-04-212-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If it is statically known that eval() will converge in one delta cycle (that is, the second commit() will always return `false`) because the design contains no feedback or buffered wires, then there is no need to run the second delta cycle at all. After this commit, the case where eval() always converges immediately is detected and the second delta cycle is omitted. As a result, Minerva SRAM SoC runs ~25% faster.
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