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author | Asu <sdelang@sdelang.fr> | 2020-04-22 20:50:13 +0200 |
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committer | Asu <sdelang@sdelang.fr> | 2020-04-22 20:53:12 +0200 |
commit | dc77563a6a0b0a812fa006a286e0ec6e091dbd3a (patch) | |
tree | a09e3a6381cb18d8d8c0e30b94017ead6d987f00 | |
parent | db27f2f3786fa867bf7524aff6a5b72c89932620 (diff) | |
download | yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.tar.gz yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.tar.bz2 yosys-dc77563a6a0b0a812fa006a286e0ec6e091dbd3a.zip |
cxxrtl: keep the memory write queue sorted on insertion.
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.
The Minerva SRAM SoC runs ~7% faster as a result.
-rw-r--r-- | backends/cxxrtl/cxxrtl.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index b79bbbc72..701510b7f 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -641,13 +641,15 @@ struct memory { void update(size_t index, const value<Width> &val, const value<Width> &mask, int priority = 0) { assert(index < data.size()); - write_queue.emplace_back(write { index, val, mask, priority }); + // Queue up the write while keeping the queue sorted by priority. + write_queue.insert( + std::upper_bound(write_queue.begin(), write_queue.end(), priority, + [](const int a, const write& b) { return a < b.priority; }), + write { index, val, mask, priority }); } bool commit() { bool changed = false; - std::sort(write_queue.begin(), write_queue.end(), - [](const write &a, const write &b) { return a.priority < b.priority; }); for (const write &entry : write_queue) { value<Width> elem = data[entry.index]; elem = elem.update(entry.val, entry.mask); |