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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:50:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 17:50:30 -0700 |
| commit | 988d47af8533a0c7728095862dbc6a7311c1f8b7 (patch) | |
| tree | 1574fa5d122982cdf43ae120630eb5c82bda35f3 | |
| parent | 592baebd22ab1c80512b6f91926d90b33393285e (diff) | |
| download | yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.tar.gz yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.tar.bz2 yosys-988d47af8533a0c7728095862dbc6a7311c1f8b7.zip | |
tests: read +/xilinx/cell_sim.v before xilinx_dsp test
| -rw-r--r-- | tests/arch/xilinx/xilinx_dsp.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys index 3b9f52930..59d8296ab 100644 --- a/tests/arch/xilinx/xilinx_dsp.ys +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -8,4 +8,5 @@ assign o4 = a * b; DSP48E1 m3 (.A(a), .B(b), .P(o5)); endmodule EOT +read_verilog -lib +/xilinx/cells_sim.v xilinx_dsp |