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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 16:35:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 16:35:35 -0700 |
| commit | db09e96dff63b7b0fdb7010ad1965aaf261cbe2f (patch) | |
| tree | 4faac3e94ea85f10decc48fe4fdc815adad4fa76 | |
| parent | d2d90e4504a0fb43c35584484e0b949be7225b2b (diff) | |
| download | yosys-db09e96dff63b7b0fdb7010ad1965aaf261cbe2f.tar.gz yosys-db09e96dff63b7b0fdb7010ad1965aaf261cbe2f.tar.bz2 yosys-db09e96dff63b7b0fdb7010ad1965aaf261cbe2f.zip | |
test: ice40_dsp test to read +/ice40/cells_sim.v for default params
| -rw-r--r-- | tests/arch/ice40/ice40_dsp.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys index 250273859..b13e525fd 100644 --- a/tests/arch/ice40/ice40_dsp.ys +++ b/tests/arch/ice40/ice40_dsp.ys @@ -8,4 +8,5 @@ assign o4 = a * b; SB_MAC16 m3 (.A(a), .B(b), .O(o5)); endmodule EOT +read_verilog -lib +/ice40/cells_sim.v ice40_dsp |