| Commit message (Expand) | Author | Age | Files | Lines | ||
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| * | | | | | Merge pull request #1742 from nakengelhardt/rpc-test-again | Miodrag Milanović | 2020-03-06 | 1 | -1/+2 | |
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| | * | | | | rpc test: make frontend listen before launching yosys & introduce safeguard i... | N. Engelhardt | 2020-03-06 | 1 | -1/+2 | |
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| * | | | | Merge pull request #1739 from YosysHQ/eddie/issue1738 | Eddie Hung | 2020-03-05 | 2 | -7/+18 | |
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| | * | | | | ice40: fix specify for ICE40_{LP,U} | Eddie Hung | 2020-03-05 | 1 | -4/+4 | |
| | * | | | | tests: extend tests/arch/run-tests.sh for defines | Eddie Hung | 2020-03-05 | 1 | -3/+14 | |
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| * | | | | ice40: fix implicit signal in specify, also clamp negative times to 0 | Eddie Hung | 2020-03-04 | 1 | -22/+22 | |
| * | | | | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1 | Eddie Hung | 2020-03-04 | 4 | -109/+244 | |
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| | * | | | | xilinx: consider DSP48E1.ADREG | Eddie Hung | 2020-03-04 | 4 | -5/+8 | |
| | * | | | | xilinx: cleanup DSP48E1 handling for abc9 | Eddie Hung | 2020-03-04 | 3 | -86/+125 | |
| | * | | | | xilinx: improve specify for DSP48E1 | Eddie Hung | 2020-03-04 | 1 | -32/+116 | |
| | * | | | | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v | Eddie Hung | 2020-03-04 | 2 | -5/+14 | |
| * | | | | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc | N. Engelhardt | 2020-03-03 | 2 | -6/+39 | |
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| | * | | | | | Add -flowmap to synth and synth_ice40 | Dan Ravensloft | 2020-02-28 | 2 | -6/+39 | |
| * | | | | | | Fix bison warning for "pure-parser" option | Claire Wolf | 2020-03-03 | 1 | -1/+1 | |
| * | | | | | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 11 | -305/+388 | |
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| | * | | | | | | Change attribute search value to specify precise location instead of simple l... | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 | |
| | * | | | | | | Change attribute search value to specify precise location instead of simple l... | Alberto Gonzalez | 2020-02-24 | 1 | -2/+2 | |
| | * | | | | | | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 9 | -301/+384 | |
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| * | | | | | | Merge pull request #1681 from YosysHQ/eddie/fix1663 | Claire Wolf | 2020-03-03 | 1 | -15/+13 | |
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| | * | | | | | | verilog: instead of modifying localparam size, extend init constant expr | Eddie Hung | 2020-02-05 | 1 | -15/+13 | |
| * | | | | | | | Merge pull request #1519 from YosysHQ/eddie/submod_po | Claire Wolf | 2020-03-03 | 2 | -37/+223 | |
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| | * | | | | | | Merge branch 'master' into eddie/submod_po | Eddie Hung | 2020-02-01 | 219 | -5980/+12044 | |
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| | * | | | | | | | Add a quick testcase for unknown modules as inout | Eddie Hung | 2019-12-09 | 1 | -2/+24 | |
| | * | | | | | | | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-02 | 1 | -1/+1 | |
| * | | | | | | | | iopadmap: Look harder for already-present buffers. (#1731) | Marcelina Kościelnicka | 2020-03-02 | 2 | -16/+75 | |
| * | | | | | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 43 | -1697/+3425 | |
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| | * | | | | | | | | Remove RAMB{18,36}E1 from cells_xtra.py | Eddie Hung | 2020-02-27 | 1 | -2/+2 | |
| | * | | | | | | | | Small fixes | Eddie Hung | 2020-02-27 | 2 | -8/+8 | |
| | * | | | | | | | | Fixes for older compilers | Eddie Hung | 2020-02-27 | 2 | -2/+9 | |
| | * | | | | | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" | Eddie Hung | 2020-02-27 | 1 | -3/+9 | |
| | * | | | | | | | | ast: quiet down when deriving blackbox modules | Eddie Hung | 2020-02-27 | 2 | -12/+20 | |
| | * | | | | | | | | abc9_ops: suppress -prep_box warning for abc9_flop | Eddie Hung | 2020-02-27 | 1 | -1/+1 | |
| | * | | | | | | | | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 | |
| | * | | | | | | | | ice40: add delays to SB_CARRY | Eddie Hung | 2020-02-27 | 1 | -0/+30 | |
| | * | | | | | | | | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 | |
| | * | | | | | | | | Make TimingInfo::TimingInfo(SigBit) constructor explicit | Eddie Hung | 2020-02-27 | 3 | -8/+9 | |
| | * | | | | | | | | TimingInfo: index by (port_name,offset) | Eddie Hung | 2020-02-27 | 2 | -12/+23 | |
| | * | | | | | | | | Fix spacing | Eddie Hung | 2020-02-27 | 2 | -68/+68 | |
| | * | | | | | | | | More +/ice40/cells_sim.v fixes | Eddie Hung | 2020-02-27 | 1 | -27/+27 | |
| | * | | | | | | | | Cleanup tests | Eddie Hung | 2020-02-27 | 2 | -1/+1 | |
| | * | | | | | | | | Update bug1630.ys to use -lut 4 instead of lut file | Eddie Hung | 2020-02-27 | 1 | -1/+1 | |
| | * | | | | | | | | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 | |
| | * | | | | | | | | abc9_ops: still emit delay table even box has no timing | Eddie Hung | 2020-02-27 | 1 | -3/+1 | |
| | * | | | | | | | | write_xaiger: add comment about arrival times of flop outputs | Eddie Hung | 2020-02-27 | 1 | -0/+1 | |
| | * | | | | | | | | abc9_ops: demote lack of box timing info to warning | Eddie Hung | 2020-02-27 | 1 | -2/+4 | |
| | * | | | | | | | | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 6 | -651/+530 | |
| | * | | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 2 | -25/+22 | |
| | * | | | | | | | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 3 | -97/+65 | |
| | * | | | | | | | | abc9_ops: add and use new TimingInfo struct | Eddie Hung | 2020-02-27 | 2 | -70/+214 | |
| | * | | | | | | | | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 | |
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index : iCE40/yosys | |
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