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* Missing endmoduleEddie Hung2019-11-221-0/+1
* write_xaiger to not use module POs but only write outputs if drivenEddie Hung2019-11-211-11/+23
* When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
* Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-215-16/+55
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| * Add a equiv test tooEddie Hung2019-11-192-0/+23
| * Add two testsEddie Hung2019-11-191-0/+12
| * abc9 to support async flops $_DFF_[NP][NP][01]_Eddie Hung2019-11-191-1/+2
| * Do not drop async control signals in abc_map.vEddie Hung2019-11-191-12/+16
* | Add testEddie Hung2019-11-211-1/+6
* | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
* | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
* | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
* | Add multi clock testEddie Hung2019-11-201-0/+5
* | Fix INIT valuesEddie Hung2019-11-201-4/+4
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-19228-24028/+35109
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| * Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-1927-89/+841
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| | * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| | * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| | * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1615-47/+913
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| | * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-112-4/+15
| | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1129-23010/+30701
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| | * | | fix wide lutsPepijn de Vos2019-11-062-19/+22
| | * | | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
| | * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| | * | | add tristate buffer and testPepijn de Vos2019-10-283-2/+21
| | * | | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
| | * | | actually run the gowin testsPepijn de Vos2019-10-281-0/+1
| | * | | More formattingPepijn de Vos2019-10-281-55/+49
| | * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| | * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| | * | | add wide lutsPepijn de Vos2019-10-283-36/+119
| | * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| | * | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
| | * | | Add some testsPepijn de Vos2019-10-2110-0/+224
| | * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| | * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
| | * | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
| | * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
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| | * | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
| | * | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | * | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
| | * | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
| | * | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
| | * | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
| | * | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
| | * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
| | * | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
| | * | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
| | * | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
| | * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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