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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-20 13:28:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-20 13:28:55 -0800 |
| commit | cd9e830b67fdffcae88dba095548995a30988fa4 (patch) | |
| tree | 6ae49eedffc8c02727c9b42bdd8294f04e70256f | |
| parent | df63d75ff35e1441360a4b28a12b32b3d00f1190 (diff) | |
| download | yosys-cd9e830b67fdffcae88dba095548995a30988fa4.tar.gz yosys-cd9e830b67fdffcae88dba095548995a30988fa4.tar.bz2 yosys-cd9e830b67fdffcae88dba095548995a30988fa4.zip | |
Add multi clock test
| -rw-r--r-- | tests/simple_abc9/abc9.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 64b625efe..1844bac20 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -267,3 +267,8 @@ module abc9_test026(output [3:0] o, p); assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule + +module abc9_test029(input clk1, clk2, input d, output reg q1, q2); +always @(posedge clk1) q1 <= d; +always @(negedge clk2) q2 <= q1; +endmodule |