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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 16:08:13 +0200 |
|---|---|---|
| committer | Pepijn de Vos <pepijndevos@gmail.com> | 2019-10-21 16:08:13 +0200 |
| commit | 03457ee13e36574add688a9c2c5c0641a4d6df05 (patch) | |
| tree | 74053c2d769e6c33fe4bb7748406e204d54c7607 | |
| parent | 8a2699c40c9b60d28ab69c1e87629b467ccc9890 (diff) | |
| download | yosys-03457ee13e36574add688a9c2c5c0641a4d6df05.tar.gz yosys-03457ee13e36574add688a9c2c5c0641a4d6df05.tar.bz2 yosys-03457ee13e36574add688a9c2c5c0641a4d6df05.zip | |
add a few more missing dff
| -rw-r--r-- | techlibs/gowin/cells_map.v | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index e485feebd..425cf7f59 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,10 +1,3 @@ -// TODO add these DFF types -// Primitive Description -// DFFSE D Flip-Flop with Clock Enable and Synchronous Set -// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset - -// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set -// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset //TODO all DFF* have INIT // DFFN D Flip-Flop with Negative-Edge Clock @@ -28,6 +21,14 @@ module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset +module \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule +module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule + +// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset +module \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule +module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule + // DFFS D Flip-Flop with Synchronous Set module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule @@ -36,6 +37,14 @@ module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule +// DFFSE D Flip-Flop with Clock Enable and Synchronous Set +module \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule +module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule + +// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set +module \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule +module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule + // DFFP D Flip-Flop with Asynchronous Preset module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule |