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* Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-0/+31
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| * Fix multiple driver issueEddie Hung2019-11-271-2/+7
| * Add multiple driver testcaseEddie Hung2019-11-271-0/+31
* | Fix multiple driver issueEddie Hung2019-11-271-2/+7
* | Add comment, use sigmapEddie Hung2019-11-271-2/+2
* | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-275-7/+100
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| * \ Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-272-3/+72
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| | * | No need for -abc9Eddie Hung2019-11-261-1/+1
| | * | Add citationEddie Hung2019-11-261-0/+1
| | * | Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
| | * | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
| * | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
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| | * | | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
| * | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-272-4/+24
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| | * | | | opt_share: Fix handling of fine cells.Marcin Koƛcielnicki2019-11-272-4/+24
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| * | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improveEddie Hung2019-11-272-22/+5
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* | | | | ean call after abc{,9}Eddie Hung2019-11-271-1/+2
* | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-7/+3
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| * | | | Do not replace constants with same wireEddie Hung2019-11-271-7/+3
* | | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-274-34/+30
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| * | | | latch -> boxEddie Hung2019-11-261-1/+1
| * | | | Remove notesEddie Hung2019-11-261-9/+0
| * | | | Fold loopEddie Hung2019-11-261-6/+3
| * | | | Do not sigmap keep bits inside write_xaigerEddie Hung2019-11-261-1/+1
| * | | | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
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| * | | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Koƛcielnicki2019-11-263-25/+30
* | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-270-0/+0
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| * | | | clkpart to analyse async flops tooEddie Hung2019-11-251-0/+8
* | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-272-49/+94
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| * | | | CleanupEddie Hung2019-11-271-5/+3
| * | | | Check for nullptrEddie Hung2019-11-271-1/+1
| * | | | Stray log_dumpEddie Hung2019-11-271-1/+0
| * | | | Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-272-42/+76
| * | | | Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
| * | | | Fix wire widthEddie Hung2019-11-261-2/+2
| * | | | Fix submod -hiddenEddie Hung2019-11-261-5/+6
| * | | | Add -hidden option to submodEddie Hung2019-11-261-11/+25
| * | | | Update docs with bullet pointsEddie Hung2019-11-261-10/+9
| * | | | Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
| * | | | Add testcase where \init is copiedEddie Hung2019-11-251-0/+18
* | | | | Merge branch 'master' into xaig_dffEddie Hung2019-11-260-0/+0
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| * \ \ \ \ Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-11-22312-25148/+44916
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| * | | | | | Fix typoEddie Hung2019-09-271-1/+1
* | | | | | | xaiger: do not promote output wiresEddie Hung2019-11-261-5/+0
* | | | | | | Move 'clean' from map_luts to finalizeEddie Hung2019-11-261-1/+1
* | | | | | | Fix submod -hiddenEddie Hung2019-11-261-5/+6
* | | | | | | clkpart to use 'submod -hidden'Eddie Hung2019-11-261-1/+1
* | | | | | | Add -hidden option to submodEddie Hung2019-11-261-20/+40
* | | | | | | Fold loopEddie Hung2019-11-251-6/+3