iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Disable RAM16X1D match rule; carry-over from LUT4 arches	Eddie Hung	2019-12-13	1	-6/+9
*	RAM64M8 to also have [5:0] for address	Eddie Hung	2019-12-13	1	-8/+8
*	Remove extraneous synth_xilinx call	Eddie Hung	2019-12-12	1	-2/+0
*	Add tests for these new models	Eddie Hung	2019-12-12	1	-0/+40
*	Add RAM32X6SDP and RAM64X3SDP modes	Eddie Hung	2019-12-12	2	-8/+120
*	Fix RAM64M model to have 6 bit address bus	Eddie Hung	2019-12-12	1	-4/+4
*	Add #1460 testcase	Eddie Hung	2019-12-12	1	-0/+34
*	Add memory rules for RAM16X1D, RAM32M, RAM64M	Eddie Hung	2019-12-12	2	-0/+168
*	Rename memory tests to lutram, add more xilinx tests	Eddie Hung	2019-12-12	9	-53/+156
*	abc9_map.v: fix Xilinx LUTRAM	Eddie Hung	2019-12-12	1	-6/+6
*	Update README.md :: abc_ -> abc9_	Eddie Hung	2019-12-11	1	-3/+3
*	Fix bitwidth mismatch; suppresses iverilog warning	Eddie Hung	2019-12-11	1	-4/+4
*	Merge pull request #1564 from ZirconiumX/intel_housekeeping	David Shah	2019-12-11	8	-6/+6
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\| *	synth_intel: a10gx -> arria10gx	Dan Ravensloft	2019-12-10	5	-4/+4
\| *	synth_intel: cyclone10 -> cyclone10lp	Dan Ravensloft	2019-12-10	5	-4/+4
* \|	Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr	Eddie Hung	2019-12-09	8	-51/+225
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\| * \|	ice40_opt to restore attributes/name when unwrapping	Eddie Hung	2019-12-09	1	-0/+15
\| * \|	ice40_wrapcarry -unwrap to preserve 'src' attribute	Eddie Hung	2019-12-09	1	-1/+9
\| * \|	unmap $__ICE40_CARRY_WRAPPER in test	Eddie Hung	2019-12-09	1	-1/+21
\| * \|	-unwrap to create $lut not SB_LUT4 for opt_lut	Eddie Hung	2019-12-09	1	-7/+5
\| * \|	Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4	Eddie Hung	2019-12-09	2	-8/+12
\| * \|	ice40_wrapcarry to really preserve attributes via -unwrap option	Eddie Hung	2019-12-09	4	-39/+61
\| * \|	Drop keep=0 attributes on SB_CARRY	Eddie Hung	2019-12-06	2	-2/+10
\| * \|	Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-12-05	1	-0/+1
\| * \|	Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER	Eddie Hung	2019-12-05	1	-0/+30
\| * \|	Check SB_CARRY name also preserved	Eddie Hung	2019-12-03	1	-0/+1
\| * \|	$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve	Eddie Hung	2019-12-03	1	-1/+1
\| * \|	ice40_opt to ignore (* keep *) -ed cells	Eddie Hung	2019-12-03	1	-0/+5
\| * \|	ice40_wrapcarry to preserve SB_CARRY's attributes	Eddie Hung	2019-12-03	1	-0/+2
\| * \|	Add testcase	Eddie Hung	2019-12-03	1	-0/+60
* \| \|	Merge pull request #1555 from antmicro/fix-macc-xilinx-test	Eddie Hung	2019-12-06	1	-1/+1
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\| * \| \|	tests: arch: xilinx: Change order of arguments in macc.sh	Jan Kowalewski	2019-12-06	1	-1/+1
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* \| \|	Merge pull request #1551 from whitequark/manual-cell-operands	Clifford Wolf	2019-12-05	3	-43/+82
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\| * \|	kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.	whitequark	2019-12-04	2	-8/+26
\| * \|	manual: document behavior of many comb cells more precisely.	whitequark	2019-12-04	1	-35/+56
* \| \|	xilinx: Add tristate buffer mapping. (#1528)	Marcin Kościelnicki	2019-12-04	2	-9/+16
* \| \|	iopadmap: Refactor and fix tristate buffer mapping. (#1527)	Marcin Kościelnicki	2019-12-04	2	-146/+196
* \| \|	xilinx: Add models for LUTRAM cells. (#1537)	Marcin Kościelnicki	2019-12-04	3	-624/+831
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* \|	Merge pull request #1524 from pepijndevos/gowindffinit	Clifford Wolf	2019-12-03	5	-114/+571
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\| * \|	update test	Pepijn de Vos	2019-12-03	1	-2/+3
\| * \|	Use -match-init to not synth contradicting init values	Pepijn de Vos	2019-12-03	2	-11/+13
\| * \|	attempt to fix formatting	Pepijn de Vos	2019-11-25	2	-292/+292
\| * \|	gowin: add and test dff init values	Pepijn de Vos	2019-11-25	4	-41/+495
* \| \|	Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix	David Shah	2019-12-02	2	-29/+46
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\| * \| \|	abc9: Fix breaking of SCCs	David Shah	2019-12-01	2	-29/+46
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* \| \|	Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check	Clifford Wolf	2019-12-01	1	-0/+4
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\| * \|	read_ilang: do bounds checking on bit indices	Marcin Kościelnicki	2019-11-27	1	-0/+4
* \| \|	Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll	Miodrag Milanović	2019-11-29	2	-0/+21
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\| * \| \|	xilinx: Add missing blackbox cell for BUFPLL.	Marcin Kościelnicki	2019-11-29	2	-0/+21
* \| \| \|	Revert "Fold loop"	Eddie Hung	2019-11-27	1	-3/+6
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