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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 18:52:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 18:52:03 -0800 |
| commit | 50e0c835606a94c825079a63fc026c906c9985e0 (patch) | |
| tree | 4347fee988aa882b1b640df4fbd1abbf585c2bbf | |
| parent | 037d1a03df20b9c445790728bb80e1818d1edafa (diff) | |
| download | yosys-50e0c835606a94c825079a63fc026c906c9985e0.tar.gz yosys-50e0c835606a94c825079a63fc026c906c9985e0.tar.bz2 yosys-50e0c835606a94c825079a63fc026c906c9985e0.zip | |
Fix RAM64M model to have 6 bit address bus
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3ed0759db..56eb782c6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1185,10 +1185,10 @@ module RAM64M ( output DOB, output DOC, output DOD, - input [4:0] ADDRA, - input [4:0] ADDRB, - input [4:0] ADDRC, - input [4:0] ADDRD, + input [5:0] ADDRA, + input [5:0] ADDRB, + input [5:0] ADDRC, + input [5:0] ADDRD, input DIA, input DIB, input DIC, |