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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 12:45:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 12:45:22 -0800 |
| commit | 500ed9b501386b38faf6388b43c42abdbc0ee3ec (patch) | |
| tree | b62f38613257e26e65a9c21999208cf5a3a5438c | |
| parent | e05372778a26e5cbc5166f208eddc6a1b42ed198 (diff) | |
| download | yosys-500ed9b501386b38faf6388b43c42abdbc0ee3ec.tar.gz yosys-500ed9b501386b38faf6388b43c42abdbc0ee3ec.tar.bz2 yosys-500ed9b501386b38faf6388b43c42abdbc0ee3ec.zip | |
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.cc | 18 | ||||
| -rw-r--r-- | techlibs/ice40/arith_map.v | 2 |
2 files changed, 12 insertions, 8 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index 522c8c363..8c953308a 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -111,20 +111,24 @@ struct Ice40WrapCarryPass : public Pass { auto carry = module->addCell(NEW_ID, ID(SB_CARRY)); carry->setPort(ID(I0), cell->getPort(ID(A))); carry->setPort(ID(I1), cell->getPort(ID(B))); - carry->setPort(ID(CI), cell->getPort(ID(CO))); + carry->setPort(ID(CI), cell->getPort(ID(CI))); + carry->setPort(ID(CO), cell->getPort(ID(CO))); module->swap_names(carry, cell); - auto lut = module->addCell(cell->attributes.at(ID(SB_LUT4.name)).decode_string(), ID(SB_LUT4)); - lut->setParam(ID(WIDTH), 4); - lut->setParam(ID(LUT), cell->getParam(ID(LUT))); - lut->setPort(ID(A), { cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), cell->getPort(ID(I3)) }); - lut->setPort(ID(Y), cell->getPort(ID(O))); + auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string(); + auto lut = module->addCell(lut_name, ID(SB_LUT4)); + lut->setParam(ID(LUT_INIT), cell->getParam(ID(LUT))); + lut->setPort(ID(I0), cell->getPort(ID(I0))); + lut->setPort(ID(I1), cell->getPort(ID(A))); + lut->setPort(ID(I2), cell->getPort(ID(B))); + lut->setPort(ID(I3), cell->getPort(ID(I3))); + lut->setPort(ID(O), cell->getPort(ID(O))); for (const auto &a : cell->attributes) if (a.first.begins_with("\\SB_CARRY.\\")) carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second; else if (a.first.begins_with("\\SB_LUT4.\\")) lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; - else if (a.first.in(ID(SB_LUT4.name), ID::keep)) + else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived), ID(src))) continue; else log_abort(); diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index 26b24db9e..00a07247b 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); // A[2]: 1111 0000 1111 0000 // A[3]: 1111 1111 0000 0000 .LUT(16'b 0110_1001_1001_0110) - ) fadd ( + ) carry ( .A(AA[i]), .B(BB[i]), .CI(C[i]), |