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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 17:27:47 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-06 17:27:47 -0800 |
| commit | 946d5854c0b2e63a3757a0fbdf41276255967bc8 (patch) | |
| tree | 3c0edca8928e11f68724e14d2128421fe8923f60 | |
| parent | a7e0cca48003dbb212326c37c0b8a5580c2e6d2c (diff) | |
| download | yosys-946d5854c0b2e63a3757a0fbdf41276255967bc8.tar.gz yosys-946d5854c0b2e63a3757a0fbdf41276255967bc8.tar.bz2 yosys-946d5854c0b2e63a3757a0fbdf41276255967bc8.zip | |
Drop keep=0 attributes on SB_CARRY
| -rw-r--r-- | passes/pmgen/ice40_wrapcarry.cc | 8 | ||||
| -rw-r--r-- | tests/arch/ice40/wrapcarry.ys | 4 |
2 files changed, 10 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index b84790d8f..8b3cf38bb 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -51,6 +51,9 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT")); cell->attributes = std::move(st.carry->attributes); + auto it = cell->attributes.find(ID::keep); + if (it != cell->attributes.end() && !it->second.as_bool()) + cell->attributes.erase(it); cell->attributes.insert(st.lut->attributes.begin(), st.lut->attributes.end()); pm.autoremove(st.carry); @@ -69,6 +72,11 @@ struct Ice40WrapCarryPass : public Pass { log("into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology\n"); log("mapping."); log("\n"); + log("Attributes on both cells will be merged, with SB_CARRY attributes having priority\n"); + log("over SB_LUT4 attributes, except when (* keep *) attributes present on the SB_CARRY4\n"); + log("that logically evaluate to false will be dropped (thus allowing the keep attribute,\n"); + log("if any, on the SB_LUT4 to be adopted).\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys index a4b0d357a..579335b27 100644 --- a/tests/arch/ice40/wrapcarry.ys +++ b/tests/arch/ice40/wrapcarry.ys @@ -24,7 +24,7 @@ select -assert-count 1 t:$__ICE40_CARRY_WRAPPER design -reset read_verilog <<EOT module top(input A, B, CI, output O, CO); - (* foo = "bar", answer = 42 *) + (* foo = "bar", answer = 42, keep=0 *) SB_CARRY carry ( .I0(A), .I1(B), @@ -47,6 +47,6 @@ EOT ice40_wrapcarry select -assert-count 1 t:$__ICE40_CARRY_WRAPPER select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d -select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i +select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i techmap -map +/ice40/cells_map.v #TODO: Check unwrapped attributes |