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* anlogic: support BRAM mappingIcenowy Zheng2021-12-178-2/+283
| | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Bump versiongithub-actions[bot]2021-12-171-1/+1
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* Merge pull request #3115 from whitequark/issue-3112Catherine2021-12-161-3/+4
|\ | | | | cxxrtl: demote wires not inlinable only in debug_eval to locals
| * cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
| | | | | | | | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network>
* | Merge pull request #3114 from whitequark/issue-3113Catherine2021-12-161-1/+1
|\ \ | | | | | | bugpoint: avoid infinite loop between -connections and -wires
| * | bugpoint: avoid infinite loop between -connections and -wires.Catherine2021-12-151-1/+1
| | | | | | | | | | | | Fixes #3113.
* | | preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-152-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* | | Bump versiongithub-actions[bot]2021-12-151-1/+1
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* | | Merge pull request #3111 from whitequark/issue-3110Catherine2021-12-141-1/+2
|\| | | | | | | | Fix null pointer dereference after failing to extract DFF from memory
| * | Fix null pointer dereference after failing to extract DFF from memory.Catherine2021-12-141-1/+2
| |/ | | | | | | Fixes #3110.
* / Hotfix for run_shell auto-detectionClaire Xenia Wolf2021-12-141-0/+3
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Bump versiongithub-actions[bot]2021-12-141-1/+1
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* Merge pull request #3108 from YosysHQ/claire/verificdefsClaire Xen2021-12-131-1/+2
|\ | | | | Add YOSYS to the implicitly defined verilog macros in verific
| * Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Bump versiongithub-actions[bot]2021-12-131-1/+1
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* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-123-1/+214
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2Catherine2021-12-122-108/+80
|\ | | | | cxxrtl: preserve interior memory pointers across reset
| * cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
| * cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | | | | | This makes the depth properly immutable.
* | Bump versiongithub-actions[bot]2021-12-121-1/+1
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* | Fix unused param warning with ENABLE_NDEBUG.Marcelina Kościelnicka2021-12-121-1/+1
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* | rtlil: Dump empty connections when whole module is selected.Marcelina Kościelnicka2021-12-121-2/+2
| | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing.
* | Merge pull request #3103 from whitequark/write_verilog-more-zero-width-valuesCatherine2021-12-111-1/+2
|\ \ | |/ |/| write_verilog: dump zero width sigspecs correctly
| * write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
|/ | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.
* Bump versiongithub-actions[bot]2021-12-111-1/+1
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* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
|\ | | | | Fix verific import of enum values with x and/or z
| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3097 from YosysHQ/modportMiodrag Milanović2021-12-101-2/+12
|\ \ | |/ |/| If direction NONE use that from first bit
| * Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | Ad-hoc fixes/improvements
| * If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* | Merge pull request #3099 from YosysHQ/claire/readargsClaire Xen2021-12-109-41/+52
|\ \ | | | | | | Use "read" command to parse HDL files from Yosys command-line
| * | Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
|/ / | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2021-12-091-1/+1
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* | opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-092-12/+2
|/ | | | This is a fixed version of #3072.
* Bump versiongithub-actions[bot]2021-12-041-1/+1
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* Next dev cycleMiodrag Milanovic2021-12-032-2/+5
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* Release version 0.12Miodrag Milanovic2021-12-032-3/+3
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* Update manualMiodrag Milanovic2021-12-031-22/+181
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* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
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* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
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* Bump versiongithub-actions[bot]2021-12-021-1/+1
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* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-012-0/+22
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* Bump versiongithub-actions[bot]2021-11-261-1/+1
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* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
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* sta: very crude static timing analysis passLofty2021-11-259-62/+502
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Bump versiongithub-actions[bot]2021-11-181-1/+1
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* Merge pull request #3080 from YosysHQ/micko/init_wireMiodrag Milanović2021-11-171-4/+6
|\ | | | | Give initial wire unique ID, fixes #2914
| * Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
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