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Instead of INIT param on cells, use initial statement with hier ref as
Eddie Hung
2019-02-17
1
-18
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+13
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Revert "Add INIT parameter to all ff/latch cells"
Eddie Hung
2019-02-17
2
-86
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+43
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Merge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung
2019-02-17
9
-100
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+345
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Merge pull request #811 from ucb-bar/firrtlfixes
Clifford Wolf
2019-02-17
6
-56
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+298
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Removed unused variables, functions.
Jim Lawson
2019-02-15
1
-20
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+0
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Append (instead of over-writing) EXTRA_FLAGS
Jim Lawson
2019-02-15
1
-1
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+1
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Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
5
-55
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+317
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Fix sign handling of real constants
Clifford Wolf
2019-02-13
1
-5
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+4
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Merge pull request #802 from whitequark/write_verilog_async_mem_ports
Clifford Wolf
2019-02-12
1
-38
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+41
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write_verilog: correctly emit asynchronous transparent ports.
whitequark
2019-01-29
1
-38
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+41
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Merge pull request #806 from daveshah1/fsm_opt_no_reset
Clifford Wolf
2019-02-12
1
-1
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+2
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fsm_opt: Fix runtime error for FSMs without a reset state
David Shah
2019-02-07
1
-1
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+2
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Cope WIDTH of ff/latch cells is default of zero
Eddie Hung
2019-02-06
1
-6
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+6
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Remove check for cell->name[0] == '$'
Eddie Hung
2019-02-06
1
-1
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+1
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Refactor
Eddie Hung
2019-02-06
1
-21
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+5
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write_verilog to cope with init attr on q when -noexpr
Eddie Hung
2019-02-06
1
-2
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+32
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Add INIT parameter to all ff/latch cells
Eddie Hung
2019-02-06
2
-43
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+86
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Add tests for simple cases using defparam
Eddie Hung
2019-02-06
1
-0
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+21
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Add -B option to autotest.sh to append to backend_opts
Eddie Hung
2019-02-06
1
-2
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+4
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Extend testcase
Eddie Hung
2019-02-06
1
-2
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+34
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Add testcase
Eddie Hung
2019-02-06
1
-0
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+10
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Add missing blackslash-to-slash convertion to smtio.py (matching Smt2Worker::...
Clifford Wolf
2019-02-06
1
-1
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+1
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Merge pull request #798 from mmicko/master
Clifford Wolf
2019-01-27
1
-1
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+1
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Fixed Anlogic simulation model
Miodrag Milanovic
2019-01-25
1
-1
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+1
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Merge pull request #800 from whitequark/write_verilog_tribuf
Clifford Wolf
2019-01-27
1
-0
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+12
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write_verilog: write $tribuf cell as ternary.
whitequark
2019-01-27
1
-0
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+12
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Merge branch 'whitequark-write_verilog_keyword'
Clifford Wolf
2019-01-27
5
-69
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+27
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Remove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf
2019-01-27
4
-69
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+0
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write_verilog: escape names that match SystemVerilog keywords.
whitequark
2019-01-27
1
-0
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+27
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Merge pull request #796 from whitequark/proc_clean_typo
David Shah
2019-01-25
1
-1
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+1
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proc_clean: fix critical typo.
whitequark
2019-01-23
1
-1
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+1
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Merge pull request #793 from whitequark/proc_clean_fix_fully_def
Clifford Wolf
2019-01-19
1
-1
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+7
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proc_clean: fix fully def check to consider compare/signal length.
whitequark
2019-01-18
1
-1
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+7
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Cleanups in igloo2 example design
Clifford Wolf
2019-01-17
6
-7
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+4
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Add SF2 IO buffer insertion
Clifford Wolf
2019-01-17
6
-3
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+171
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Improve Igloo2 example
Clifford Wolf
2019-01-17
8
-22
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+41
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Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf
2019-01-17
1
-2
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+17
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Add "write_edif -gndvccy"
Clifford Wolf
2019-01-17
1
-5
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+13
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Add optional nullstr argument to log_id()
Clifford Wolf
2019-01-15
1
-1
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+3
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Fix handling of $shiftx in Verilog back-end
Clifford Wolf
2019-01-15
1
-3
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+6
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Merge pull request #788 from whitequark/master
Clifford Wolf
2019-01-15
1
-5
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+17
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manual: document some gates.
whitequark
2019-01-14
1
-9
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+11
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manual: explain $tribuf cell.
whitequark
2019-01-14
1
-0
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+10
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Merge pull request #787 from whitequark/flowmap_relax
Clifford Wolf
2019-01-15
7
-35
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+776
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flowmap: clean up terminology.
whitequark
2019-01-08
1
-17
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+18
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flowmap: implement depth relaxation.
whitequark
2019-01-08
7
-22
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+762
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Improve igloo2 example
Clifford Wolf
2019-01-08
4
-5
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+29
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Fix typo in manual
Clifford Wolf
2019-01-07
1
-1
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+1
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Bugfix in $memrd sharing
Clifford Wolf
2019-01-07
1
-2
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+6
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Merge pull request #782 from whitequark/flowmap_dfs
Clifford Wolf
2019-01-07
3
-124
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+243
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