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* verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-2110-47/+124
* Bump versionYosys Bot2021-02-181-1/+1
* Merge pull request #2590 from RobertBaruch/fix_fast_sop_modeClaire Xen2021-02-171-1/+1
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| * Fixes command line for abc pass in -fast -sop modeRobert Baruch2021-02-161-1/+1
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* Bump versionYosys Bot2021-02-161-1/+1
* Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
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| * Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
* | Bump versionYosys Bot2021-02-131-1/+1
* | Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
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| * | nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
* | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
* | | Bump versionYosys Bot2021-02-121-1/+1
* | | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-114-72/+176
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| * | | verilog: refactored constant function evaluationZachary Snow2021-02-044-72/+176
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* | | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-113-4/+29
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| * | | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-073-4/+29
* | | | Merge pull request #2584 from antmicro/atom_type_signednessZachary Snow2021-02-112-4/+23
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| * | | Add missing is_signed to type_atomKamil Rakoczy2021-02-112-4/+23
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* | | Bump versionYosys Bot2021-02-071-1/+1
* | | Merge pull request #2576 from zachjs/port-bind-sign-uniopwhitequark2021-02-063-8/+33
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| * | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-053-8/+33
* | | | Bump versionYosys Bot2021-02-061-1/+1
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* | | Merge pull request #2572 from antmicro/check-labelswhitequark2021-02-052-0/+28
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| * | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-042-0/+28
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* / / Bump versionYosys Bot2021-02-051-1/+1
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* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0433-258/+779
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| * | verilog: significant block scoping improvementsZachary Snow2021-01-3133-258/+779
* | | Bump versionYosys Bot2021-02-041-1/+1
* | | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
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| * | | Fix begin/end in generatedalance2020-11-112-7/+4
* | | | Bump versionYosys Bot2021-01-311-1/+1
* | | | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
* | | | Bump versionYosys Bot2021-01-301-1/+1
* | | | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
* | | | Merge pull request #2564 from whitequark/flatten-improve-errorwhitequark2021-01-291-1/+1
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| * | | | flatten: clarify confusing error message.whitequark2021-01-261-1/+1
* | | | | Bump versionYosys Bot2021-01-291-1/+1
* | | | | Merge pull request #2569 from zachjs/macro-arg-surrounding-spaceswhitequark2021-01-282-1/+25
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| * | | | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-282-1/+25
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* | | | | Merge pull request #2535 from Ravenslofty/scc-specifyClaire Xen2021-01-282-18/+61
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| * | | | scc: Add -specify option to find loops in boxesDan Ravensloft2021-01-262-18/+61
* | | | | Bump versionYosys Bot2021-01-271-1/+1
* | | | | xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-273-4/+51
* | | | | xilinx: Add FDRSE_1, FDCPE_1.Marcelina Kościelnicka2021-01-271-0/+80
* | | | | Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
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| * | | | | cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
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* | | | | Merge pull request #2544 from modwizcode/fix-clockwhitequark2021-01-261-7/+15
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| * | | | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
| * | | | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
* | | | | Bump versionYosys Bot2021-01-261-1/+1