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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2021-02-04 12:12:59 +0100 |
|---|---|---|
| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2021-02-04 17:16:30 +0100 |
| commit | 98c4feb72ff52f12aadd34b0deccb819d701ff2c (patch) | |
| tree | a1d186a2cf2830f84711ce4d097154f30313310b | |
| parent | baf1875307f1608762169d3037ba005da88b201e (diff) | |
| download | yosys-98c4feb72ff52f12aadd34b0deccb819d701ff2c.tar.gz yosys-98c4feb72ff52f12aadd34b0deccb819d701ff2c.tar.bz2 yosys-98c4feb72ff52f12aadd34b0deccb819d701ff2c.zip | |
Add check of begin/end labels for genblock
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 | ||||
| -rw-r--r-- | tests/verilog/block_labels.ys | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 6255a4204..fb5846f7b 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2794,6 +2794,8 @@ gen_block: ast_stack.push_back(node); } module_gen_body TOK_END opt_label { exitTypeScope(); + if ($3 != NULL && $7 != NULL && *$3 != *$7) + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); delete $3; delete $7; SET_AST_NODE_LOC(ast_stack.back(), @1, @7); diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys new file mode 100644 index 000000000..e76bcf771 --- /dev/null +++ b/tests/verilog/block_labels.ys @@ -0,0 +1,26 @@ +read_verilog <<EOT +module foo; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : a +endmodule +EOT +read_verilog <<EOT +module foo2; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end +endmodule +EOT + +logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1 +read_verilog <<EOT +module foo3; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : b +endmodule +EOT |