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| author | Diego H <diego@yosyshq.com> | 2021-02-04 15:35:35 -0600 |
|---|---|---|
| committer | Diego H <diego@yosyshq.com> | 2021-02-04 15:35:35 -0600 |
| commit | c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2 (patch) | |
| tree | 6cce1e5de9997704b69df19db94d422761a4cfb0 | |
| parent | baf1875307f1608762169d3037ba005da88b201e (diff) | |
| download | yosys-c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2.tar.gz yosys-c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2.tar.bz2 yosys-c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2.zip | |
Accept disable case for SVA liveness properties.
| -rw-r--r-- | frontends/verific/verificsva.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 632043b6f..1f5da1b1d 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1759,6 +1759,11 @@ struct VerificSvaImporter clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); } + // accept in disable case + + if (clocking.disable_sig != State::S0) + sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig); + // generate fair/live cell RTLIL::Cell *c = nullptr; |