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| author | whitequark <whitequark@whitequark.org> | 2021-01-28 21:32:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-28 21:32:27 +0000 |
| commit | 74b0c385200d4282011c372d08e1e64b540d4132 (patch) | |
| tree | 53e1add099b0428b2ce59587d9e99c95102a36b0 | |
| parent | d0d7a360edb08abf4dce6e37f61eea0a6e6ef045 (diff) | |
| parent | 27257a419fe94e10f24eea916c56821e22e43cc5 (diff) | |
| download | yosys-74b0c385200d4282011c372d08e1e64b540d4132.tar.gz yosys-74b0c385200d4282011c372d08e1e64b540d4132.tar.bz2 yosys-74b0c385200d4282011c372d08e1e64b540d4132.zip | |
Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces
verilog: strip leading and trailing spaces in macro args
| -rw-r--r-- | frontends/verilog/preproc.cc | 6 | ||||
| -rw-r--r-- | tests/simple/macro_arg_surrounding_spaces.v | 20 |
2 files changed, 25 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 5a2804a41..c451c4c20 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -390,12 +390,16 @@ static void input_file(std::istream &f, std::string filename) // the argument list); false if we finished with ','. static bool read_argument(std::string &dest) { + skip_spaces(); std::vector<char> openers; for (;;) { std::string tok = next_token(true); if (tok == ")") { - if (openers.empty()) + if (openers.empty()) { + while (dest.size() && (dest.back() == ' ' || dest.back() == '\t')) + dest = dest.substr(0, dest.size() - 1); return true; + } if (openers.back() != '(') log_error("Mismatched brackets in macro argument: %c and %c.\n", openers.back(), tok[0]); diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v new file mode 100644 index 000000000..3dbb5ea01 --- /dev/null +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -0,0 +1,20 @@ +module top( + IDENT_V_, + IDENT_W_, + IDENT_X_, + IDENT_Y_, + IDENT_Z_, + IDENT_A_, + IDENT_B_, + IDENT_C_ +); + `define MACRO(dummy, x) IDENT_``x``_ + output wire IDENT_V_; + output wire `MACRO(_,W); + output wire `MACRO(_, X); + output wire `MACRO(_,Y ); + output wire `MACRO(_, Z ); + output wire `MACRO(_, A); + output wire `MACRO(_,B ); + output wire `MACRO(_, C ); +endmodule |