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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-0311-305/+388
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | line number.
| * Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | line number.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-239-301/+384
| | | | | | | | and RTLIL nodes.
* | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ | | | | | | verilog: instead of modifying localparam size, extend init constant expr
| * | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
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* | | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-032-37/+223
|\ \ \ | | | | | | | | submod: several bugfixes
| * \ \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-01219-5980/+12044
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| * | | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
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| * | | | Use pool instead of std::set for determinismEddie Hung2019-12-021-1/+1
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* | | | | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-022-16/+75
| | | | | | | | | | | | | | | | | | | | | | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* | | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0243-1697/+3425
|\ \ \ \ \ | | | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
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| * | | | | Small fixesEddie Hung2020-02-272-8/+8
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| * | | | | Fixes for older compilersEddie Hung2020-02-272-2/+9
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| * | | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
| * | | | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
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| * | | | | abc9_ops: suppress -prep_box warning for abc9_flopEddie Hung2020-02-271-1/+1
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| * | | | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
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| * | | | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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| * | | | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
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| * | | | | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-273-8/+9
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| * | | | | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-272-12/+23
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| * | | | | Fix spacingEddie Hung2020-02-272-68/+68
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| * | | | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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| * | | | | Cleanup testsEddie Hung2020-02-272-1/+1
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| * | | | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
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| * | | | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
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| * | | | | abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
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| * | | | | write_xaiger: add comment about arrival times of flop outputsEddie Hung2020-02-271-0/+1
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| * | | | | abc9_ops: demote lack of box timing info to warningEddie Hung2020-02-271-2/+4
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| * | | | | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-276-651/+530
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| * | | | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-272-25/+22
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| * | | | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-273-97/+65
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| * | | | | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-272-70/+214
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| * | | | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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| * | | | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
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| * | | | | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
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| * | | | | Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
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| * | | | | Update simple_abc9 testsEddie Hung2020-02-273-5/+8
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| * | | | | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-274-104/+114
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| * | | | | ice40: specify fixesEddie Hung2020-02-273-66/+66
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| * | | | | abc9_ops: sort LUT delays to be ascendingEddie Hung2020-02-271-1/+4
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| * | | | | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
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| * | | | | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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| * | | | | Update xilinx for ABC9Eddie Hung2020-02-273-20/+16
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| * | | | | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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| * | | | | abc9_ops: output LUT areaEddie Hung2020-02-271-6/+6
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| * | | | | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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| * | | | | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTsEddie Hung2020-02-271-18/+33
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