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Panic over. Model was elsewhere. Re-arrange for consistency
Eddie Hung
2019-10-04
5
-31
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+4
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Oops
Eddie Hung
2019-10-04
1
-1
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+1
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Ohmilord this wasn't added all this time!?!
Eddie Hung
2019-10-04
1
-0
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+29
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Change smtbmc "Warmup failed" status to "PREUNSAT"
Clifford Wolf
2019-10-03
1
-14
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+14
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Update ABC to git rev 623b5e8
Clifford Wolf
2019-10-03
1
-1
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+1
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Bump version
Clifford Wolf
2019-10-03
1
-1
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+1
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Merge pull request #1419 from YosysHQ/eddie/lazy_derive
Clifford Wolf
2019-10-03
2
-35
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+59
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Fix for svinterfaces
Eddie Hung
2019-09-30
1
-2
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+8
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module->derive() to be lazy and not touch ast if already derived
Eddie Hung
2019-09-30
2
-33
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+51
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Merge pull request #1422 from YosysHQ/eddie/aigmap_select
Clifford Wolf
2019-10-03
2
-6
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+50
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Add quick test
Eddie Hung
2019-09-30
1
-0
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+10
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Add -select option to aigmap
Eddie Hung
2019-09-30
1
-6
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+40
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Merge pull request #1429 from YosysHQ/clifford/checkmapped
Clifford Wolf
2019-10-03
2
-27
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+56
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Add "check -allow-tbuf"
Clifford Wolf
2019-10-03
1
-8
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+22
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Add "check -mapped"
Clifford Wolf
2019-10-02
2
-21
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+36
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Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
David Shah
2019-10-03
6
-2
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+184
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ecp5: Fix shuffle_enable port
David Shah
2019-10-01
1
-2
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+2
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ecp5: Add support for mapping 36-bit wide PDP BRAMs
David Shah
2019-10-01
6
-1
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+183
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Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
Eddie Hung
2019-10-02
2
-0
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+32
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Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
Eddie Hung
2019-10-02
1
-4
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+8
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Extend test with renaming cells with prefix too
Eddie Hung
2019-10-02
1
-0
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+2
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Add test
Eddie Hung
2019-09-30
1
-0
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+16
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techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
Eddie Hung
2019-09-30
1
-0
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+10
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log_dump() to support State enum
Eddie Hung
2019-10-02
3
-0
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+6
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Merge pull request #1428 from YosysHQ/clifford/fixbtor
Clifford Wolf
2019-10-02
1
-6
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+9
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Fix btor back-end to use "state" instead of "input" for undef init bits
Clifford Wolf
2019-10-02
1
-6
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+9
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Merge pull request #1426 from YosysHQ/mmicko/fix_environ
Miodrag Milanović
2019-10-01
1
-0
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+2
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Define environ, fixes #1424
Miodrag Milanovic
2019-10-01
1
-0
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+2
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Fix typo
Eddie Hung
2019-09-30
1
-1
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+1
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Update doc for equiv_opt
Eddie Hung
2019-09-30
1
-2
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+3
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Merge pull request #1406 from whitequark/connect_rpc
whitequark
2019-09-30
11
-0
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+1767
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rpc: new frontend.
whitequark
2019-09-30
9
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+744
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libs: import json11.
whitequark
2019-09-30
3
-0
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+1023
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Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
Eddie Hung
2019-09-30
1
-0
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+2
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Generate Python wrappers for inline constructors
Benedikt Tutzer
2019-09-23
1
-0
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+2
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Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
Miodrag Milanović
2019-09-30
4
-6
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+10
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Fix reading aig files on windows
Miodrag Milanovic
2019-09-29
1
-1
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+5
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Open aig frontend as binary file
Miodrag Milanovic
2019-09-29
4
-5
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+5
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Bump version
Clifford Wolf
2019-09-30
1
-1
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+1
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Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
Clifford Wolf
2019-09-30
1
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+2
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equiv_opt to call async2sync when not -multiclock like SymbiYosys
Eddie Hung
2019-09-27
1
-0
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+2
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Merge pull request #1417 from YosysHQ/clifford/fixasync2sync
Clifford Wolf
2019-09-30
1
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+1
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Fix $dlatch handling in async2sync
Clifford Wolf
2019-09-30
1
-0
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+1
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Add latch test modified from #1363
Eddie Hung
2019-09-30
2
-0
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+73
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Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
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+46
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synth_xilinx: Support latches, remove used-up FF init values.
Marcin Kościelnicki
2019-09-30
3
-2
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+77
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Merge pull request #1414 from hzeller/improve-replace-with-empty-map
Eddie Hung
2019-09-29
1
-0
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+2
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Avoid work in replace() if rules empty.
Henner Zeller
2019-09-29
1
-0
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+2
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Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
44
-281
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+6234
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Re-order
Eddie Hung
2019-09-27
2
-2
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+2
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