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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 15:34:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 15:34:04 -0700 |
| commit | 8b239ee707a2bf4a868728046d7f64c16d74aa2a (patch) | |
| tree | ecea07e276a092d36522820a6ae404eaaba56f46 | |
| parent | f2f19df2d4387ae70f5b063f2bd6e7cbdaa1ce75 (diff) | |
| download | yosys-8b239ee707a2bf4a868728046d7f64c16d74aa2a.tar.gz yosys-8b239ee707a2bf4a868728046d7f64c16d74aa2a.tar.bz2 yosys-8b239ee707a2bf4a868728046d7f64c16d74aa2a.zip | |
Add quick test
| -rw-r--r-- | tests/techmap/aigmap.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys new file mode 100644 index 000000000..a40aa39f1 --- /dev/null +++ b/tests/techmap/aigmap.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module top(input i, j, s, output o, p); +assign o = s ? j : i; +assign p = ~i; +endmodule +EOT + +select t:$mux +aigmap -select +select -assert-any % |