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* added some checks if python is enabled to make sure everything compiles if ↵Benedikt Tutzer2018-08-205-7/+12
| | | | python is disabled in the makefile
* Two passes are not allowed to have the same filenameBenedikt Tutzer2018-08-201-1/+1
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* The share directory cannot be searched when used as a Python library, only ↵Benedikt Tutzer2018-08-202-1/+8
| | | | in shell mode
* Python passes are now looked for in share/plugins and can be added by ↵Benedikt Tutzer2018-08-202-24/+5
| | | | specifying a relative or absolute path
* Fixed issue when using a python plugin in the yosys shellBenedikt Tutzer2018-08-203-4/+28
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* Python Passes can now be added with the -m option or with the plugin ↵Benedikt Tutzer2018-08-165-2/+160
| | | | command. There are still issues when run in shell mode, but they can be used just fine in a python script
* Added Wrappers for:Benedikt Tutzer2018-08-134-144/+2925
| | | | | | | | | | | | | | | -IdString -Const -CaseRule -SwitchRule -SyncRule -Process -SigChunk -SigBit -SigSpec With all their member functions as well as the remaining member functions for Cell, Wire, Module and Design and static functions of rtlil.h
* Saving id and pointer to c++ object. Object is valid only if both id and ↵Benedikt Tutzer2018-08-011-8/+29
| | | | pointer match the pair saved in the corresponding map in kernel/rtlil.cc. Otherwise, the object was destroyed in c++ and should not be accessed any more
* Setup is called automatically when the module is loaded, shutdown when ↵Benedikt Tutzer2018-08-011-16/+19
| | | | python exits
* Cleaned up commentsBenedikt Tutzer2018-08-011-9/+3
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* removed unused library and already present compiler flagBenedikt Tutzer2018-08-011-3/+3
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* Added Monitor class that can monitor all changes in a Design or in a ModuleBenedikt Tutzer2018-07-101-0/+119
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* added destructors for wires and cellsBenedikt Tutzer2018-07-102-1/+16
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* removed debug outputBenedikt Tutzer2018-07-091-1/+0
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* commands can now be run on arbitrary designs, not only on the active oneBenedikt Tutzer2018-07-091-0/+10
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* multiple designs can now exist independent from each other. ↵Benedikt Tutzer2018-07-093-45/+118
| | | | Cells/Wires/Modules can now move to a different parent without referencing issues
* Introduced namespace and removed class-prefixes to increase readabilityBenedikt Tutzer2018-06-281-163/+165
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* changed references from hash-ids to IdString namesBenedikt Tutzer2018-06-281-64/+32
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* added wrappers for Design, Modules, Cells and WiresBenedikt Tutzer2018-06-252-0/+245
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* added ENABLE_PYTHON option in build environmentBenedikt Tutzer2018-06-221-1/+10
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* Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-06-201-1/+1
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| * Merge pull request #572 from q3k/q3k/fix-protobuf-buildClifford Wolf2018-06-201-1/+1
| |\ | | | | | | Fix protobuf build
| | * Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
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* / Add automatic verific import in hierarchy commandClifford Wolf2018-06-203-1/+75
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #571 from q3k/q3k/protobuf-backendClifford Wolf2018-06-195-0/+560
|\ | | | | Add Protobuf backend
| * Add Protobuf backendSerge Bazanski2018-06-195-0/+560
| | | | | | | | Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
* | Be slightly less aggressive in "deminout" passClifford Wolf2018-06-191-4/+28
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #570 from edcote/patch-4Clifford Wolf2018-06-191-4/+4
|\ \ | |/ |/| Include module name for area summary stats
| * Include module name for area summary statsEdmond Cote2018-06-181-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
* Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #561 from udif/pr_skip_typoClifford Wolf2018-06-061-1/+1
|\ | | | | Fixed typo (sikp -> skip)
| * Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
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* Add (* gclk *) attribute supportClifford Wolf2018-06-014-1/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add setundef -anyseq / -anyconst support to -undriven modeClifford Wolf2018-06-011-3/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "setundef -anyconst"Clifford Wolf2018-06-011-20/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in handling of array instances with empty portsClifford Wolf2018-05-311-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update examples/cmos/counter.ys to use "synth" commandClifford Wolf2018-05-301-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update ABC to git rev 6df1396Clifford Wolf2018-05-301-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some cleanup code to memory_nordffClifford Wolf2018-05-281-26/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add comment to VIPER #13453 work-aroundClifford Wolf2018-05-281-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #454 from rqou/emscripten-and-abcClifford Wolf2018-05-194-15/+87
|\ | | | | Add option to statically link abc; emscripten fixes
| * Force abc to align memory to 8 bytesRobert Ou2018-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | Apparently abc has a memory pool implementation that by default returns memory that is unaligned. There is a workaround in the abc makefile that uses uname to look for "arm" specifically and then sets the alignment. However, ARM is not the only platform that requires proper alignment (e.g. emscripten does too). For now, pessimistically force the alignment for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten despite being approximately a 32-bit platform).
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