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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-19 13:47:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-19 13:47:39 +0200 |
| commit | 25c5002f8367043ca3ec7e8f5ad9c1dd53a381c2 (patch) | |
| tree | e641204de220a43a975d8bae3b3488e1ab4bcff4 | |
| parent | 0ff0ce4973db6f91b717b3771d8a9ca4cdb3a191 (diff) | |
| parent | d89560a0ba6402a8d13177909cc2c1f3b8b7c3e2 (diff) | |
| download | yosys-25c5002f8367043ca3ec7e8f5ad9c1dd53a381c2.tar.gz yosys-25c5002f8367043ca3ec7e8f5ad9c1dd53a381c2.tar.bz2 yosys-25c5002f8367043ca3ec7e8f5ad9c1dd53a381c2.zip | |
Merge pull request #570 from edcote/patch-4
Include module name for area summary stats
| -rw-r--r-- | passes/cmds/stat.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index e52a192db..f1d958a1a 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -142,7 +142,7 @@ struct statdata_t } } - void log_data() + void log_data(RTLIL::IdString mod_name, bool top_mod) { log(" Number of wires: %6d\n", num_wires); log(" Number of wire bits: %6d\n", num_wire_bits); @@ -163,7 +163,7 @@ struct statdata_t if (area != 0) { log("\n"); - log(" Chip area for this module: %f\n", area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); } } }; @@ -275,7 +275,7 @@ struct StatPass : public Pass { log("\n"); log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("\n"); - data.log_data(); + data.log_data(mod->name, false); } if (top_mod != NULL && GetSize(mod_stat) > 1) @@ -288,7 +288,7 @@ struct StatPass : public Pass { statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0); log("\n"); - data.log_data(); + data.log_data(top_mod->name, true); } log("\n"); |