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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-31 18:09:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-31 18:09:31 +0200 |
| commit | 3ab79a231b1b31f1177df2c1351643eda4e9553b (patch) | |
| tree | 7e54255751d9b97855285624695930dffc46e098 | |
| parent | 7f0548c16f64bd0c4e3bd85744cfdcf9494b4829 (diff) | |
| download | yosys-3ab79a231b1b31f1177df2c1351643eda4e9553b.tar.gz yosys-3ab79a231b1b31f1177df2c1351643eda4e9553b.tar.bz2 yosys-3ab79a231b1b31f1177df2c1351643eda4e9553b.zip | |
Bugfix in handling of array instances with empty ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 18dfa7184..bfb8e7f95 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -258,7 +258,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); int port_size = mod->wires_.at(portname)->width; - if (conn_size == port_size) + if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); |