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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-28 13:36:35 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-28 13:36:35 +0200 |
| commit | 9a946c207fd4f5e18ce464e39d7d180c29ce5c23 (patch) | |
| tree | 424664e625c30bf1ff1d9eb634a42f3613868b67 | |
| parent | 001c9f1d45749535452d082a7c92a17954b603b8 (diff) | |
| download | yosys-9a946c207fd4f5e18ce464e39d7d180c29ce5c23.tar.gz yosys-9a946c207fd4f5e18ce464e39d7d180c29ce5c23.tar.bz2 yosys-9a946c207fd4f5e18ce464e39d7d180c29ce5c23.zip | |
Add comment to VIPER #13453 work-around
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 60fa6db3b..12f2fdd7f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1395,6 +1395,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a return; } + // Use while() instead of if() to work around VIPER #13453 while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) { net = inst->GetInput(); |