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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-24 18:13:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-24 18:13:38 +0200 |
| commit | 251562a4918576bd485bcdcc908c0ac780689a77 (patch) | |
| tree | b7370ee9bc9428d52664aba93acafd973e9dc010 | |
| parent | 4d645f0fce9e3af857cb292eca719c22141d379b (diff) | |
| download | yosys-251562a4918576bd485bcdcc908c0ac780689a77.tar.gz yosys-251562a4918576bd485bcdcc908c0ac780689a77.tar.bz2 yosys-251562a4918576bd485bcdcc908c0ac780689a77.zip | |
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 7ebcbca04..19273c69a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1393,7 +1393,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a return; } - if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) + while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) { net = inst->GetInput(); inst = net->Driver();; |