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| * | | | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-278-466/+268
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| * | | | abc9_ops: assert on $specify2 propertiesEddie Hung2020-02-271-0/+3
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| * | | | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-273-51/+50
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| * | | | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-274-10/+200
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* | | | | Merge pull request #1729 from rqou/coolrunner2N. Engelhardt2020-03-023-109/+443
|\ \ \ \ \ | | | | | | | | | | | | coolrunner2 buffer cell insertion fixes
| * | | | | coolrunner2: Attempt to give wires/cells more meaningful namesR. Ou2020-03-022-23/+66
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| * | | | | coolrunner2: Fix invalid multiple fanouts of XOR/OR gatesR. Ou2020-03-021-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
| * | | | | coolrunner2: Fix packed register+input buffer insertionR. Ou2020-03-021-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads.
| * | | | | coolrunner2: Insert many more required feedthrough cellsR. Ou2020-03-013-102/+215
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* | | | | Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2Eddie Hung2020-02-291-11/+11
|\ \ \ \ \ | | | | | | | | | | | | ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
| * | | | | ystests: fix write_smt2_write_smt2_cyclic_dependency_failEddie Hung2020-02-281-11/+11
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* | | | | | Merge pull request #1726 from YosysHQ/eddie/fix1710Eddie Hung2020-02-282-9/+52
|\ \ \ \ \ \ | |/ / / / / |/| | | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary branch
| * | | | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-272-9/+52
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* / / / / Comment out log()Eddie Hung2020-02-271-1/+1
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* | | | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-274-97/+519
|\ \ \ \ | | | | | | | | | | Improve CoolRunner-II optimization by using extract_counter pass
| * | | | coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
| * | | | extract_counter: Implement extracting up countersR. Ou2020-02-171-65/+247
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| * | | | extract_counter: Add support for inverted clock enableR. Ou2020-02-171-8/+28
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| * | | | extract_counter: Fix clock enableR. Ou2020-02-171-1/+3
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| * | | | extract_counter: Fix outputting count to module portR. Ou2020-02-171-8/+20
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| * | | | extract_counter: Allow forbidding async resetR. Ou2020-02-171-2/+17
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| * | | | extract_counter: Refactor out extraction settings into structR. Ou2020-02-171-17/+43
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* | | | | Merge pull request #1708 from rqou/coolrunner2-buf-fixClaire Wolf2020-02-274-54/+163
|\ \ \ \ \ | | | | | | | | | | | | coolrunner2: Separate and improve buffer cell insertion pass
| * | | | | coolrunner2: Separate and improve buffer cell insertion passR. Ou2020-02-164-54/+163
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between.
* | | | | xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
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* | | | | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-266-2/+303
|\ \ \ \ \ | | | | | | | | | | | | Logger pass
| * | | | | Remove tests for nowMiodrag Milanovic2020-02-264-24/+0
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| * | | | | Add tests for logger passMiodrag Milanovic2020-02-234-0/+24
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| * | | | | Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6
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| * | | | | Fix line endingsMiodrag Milanovic2020-02-231-10/+10
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| * | | | | Update explanation for expect-no-warningsMiodrag Milanovic2020-02-221-1/+1
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| * | | | | Handle expect no warnings together with expectedMiodrag Milanovic2020-02-223-4/+12
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| * | | | | Check other regex parametersMiodrag Milanovic2020-02-221-15/+30
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| * | | | | check for regex errorsMiodrag Milanovic2020-02-201-16/+20
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| * | | | | Prevent double error messageMiodrag Milanovic2020-02-171-1/+3
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| * | | | | Option to expect no warningsMiodrag Milanovic2020-02-174-0/+12
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| * | | | | Add to changelogMiodrag Milanovic2020-02-171-0/+1
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| * | | | | No new error if already failingMiodrag Milanovic2020-02-171-1/+2
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| * | | | | remove whitespaceMiodrag Milanovic2020-02-141-1/+1
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| * | | | | Add expect option to logger commandMiodrag Milanovic2020-02-144-3/+113
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| * | | | | Add new logger passMiodrag Milanovic2020-02-132-0/+142
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* | | | | | Merge pull request #1715 from boqwxp/masterEddie Hung2020-02-221-2/+0
|\ \ \ \ \ \ | | | | | | | | | | | | | | Closes #1714. Fix make failure when NDEBUG=1.
| * | | | | | Closes #1714. Fix make failure when NDEBUG=1.Alberto Gonzalez2020-02-221-2/+0
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* | | | | | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-218-52/+170
|\ \ \ \ \ \ | | | | | | | | | | | | | | Improve specify parser
| * | | | | | verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * | | | | | clean: ignore specify-s inside cells when determining whether to keepEddie Hung2020-02-192-10/+35
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| * | | | | | verilog: ignore ranges too without -specifyEddie Hung2020-02-132-1/+9
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| * | | | | | verilog: improve specify support when not in -specify modeEddie Hung2020-02-133-16/+8
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| * | | | | | verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-133-5/+12
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| * | | | | | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-134-16/+52
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